State-of-the-art silicon water splitting photoelectrochemical cells employ oxide protection layers that exhibit electrical conductance in between that of dielectric insulators and electronic conductors, optimizing both built-in field and conductivity. The SiO2-like layer interposed between a deposited protective oxide film and its Si substrate plays a key role as a tunnel oxide that can dominate the total device impedance. In this report, we investigate the effects of changes in interfacial SiO2 resistance and capacitance in the oxide bilayer through both solid state leakage current and capacitance–voltage measurements and through electrochemical methods applied to water splitting cells. Modelling is performed to describe both types of data in a simple and intuitive way, allowing for insights to be developed into the connections among both the dielectric (charge storage) and conductive (charge transport) properties of bilayer protective oxides and their effects on oxygen evolution performance. Finally, atomic layer deposited (ALD) Al2O3 is studied as an insulator layer with conductivity intermediate between that of tunnel oxide SiO2 and the more conductive ALD-TiO2, to further generalize this understanding.

We report on the role of hydrogen (forming gas) post-metal annealing to passivate border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and of bias temperature stress treatments to generate/depassivate such traps. Experiments are carried out with Pd metal gates that efficiently dissociate molecular hydrogen during forming gas annealing, and they make use of InGaAs epitaxial layer substrates that are capped with arsenic after completion of their growth, to avoid unintentional oxide formation and disorder at the channel surface prior to atomic layer deposition of the Al2O3 gate dielectric. We find that forming gas anneal (FGA) greatly reduces both the interface trap density and border trap density measured in the gate stacks, but that the effectiveness of FGA for border trap passivation saturates for anneals with thermal budgets greater than 450°C/30 min. Both negative and positive bias temperature stress treatments are found to have no effect on the extracted border trap densities compared to non-treated capacitors.

We explore the electronic and transport properties out of a biased multilayer hexagonal boron nitride (h-BN) by first-principles calculations. The band gaps of multilayer h-BN decrease almost linearly with increasing perpendicular electric field, irrespective of the layer number N and stacking manner. The critical electric filed (E0) required to close the band gap decreases with the increasing N and can be approximated by E0 = 3.2 / (N − 1) (eV). We provide a quantum transport simulation of a dual-gated 4-layer h-BN with graphene electrodes. The transmission gap in this device can be effectively reduced by double gates, and a high on-off ratio of 3000 is obtained with relatively low voltage. This renders biased MLh-BN a promising channel in field effect transistor fabrication.