In this paper, we reported the mechanism of a bimodal Weibull distribution for TDDB of gate dielectric in GaN MISHEMT. It is shown that the properties of traps in the dielectric layer would have a great influence on the long time reliability and life time prediction process. 

In this study, the physical properties of F ion-implanted GaN were thoroughly studied, and the related electric-field modulation mechanisms in ion-implanted edge termination were revealed. Transmission electron microscopy results indicate that the ion-implanted region maintains a single-crystal structure even with the implantation of high-energy F ions, indicating that the high resistivity of the edge termination region is not induced by amorphization. Alternately, ion implantation-induced deep levels could compensate the electrons and lead to a highly resistive layer. In addition to the bulk effect, the direct bombardment of high-energy F ions resulted in a rough and nitrogen-deficient surface, which was confirmed via atomic force microscopy (AFM) and X-ray photoelectron spectroscopy. The implanted surface with a large density of nitrogen vacancies can accommodate electrons, and it is more conductive than the bulk in the implanted region, which is validated via spreading resistance profiling and conductive AFM measurements. Under reverse bias, the implanted surface can spread the potential in the lateral direction, whereas the acceptor traps capture electrons acting as space charges, shifting the peak electric field into the bulk region in the vertical direction. As a result, the Schottky barrier diode terminated with high-energy F ion-implanted regions exhibits a breakdown voltage of over 1.2 kV.

A ridge-channel AlGaN/GaN high-electron mobility transistor (HEMT) utilizing selective-area growth and epitaxial lateral overgrowth (ELO) technique is proposed in this work to achieve high-performance normally-off devices. It has a c-plane platform for the source and the drain contacts, and sidewalls of lattice plane for the gate contact. The sidewalls have characteristics of weak polarization and thin barrier, which are advantageous for realizing normally-off operation. Two ridge HEMTs with triangular and trapezoid channel are designed. Theoretical simulation demonstrates a threshold voltage of 0.03 V for the sidewall channel with reduced polarization and barrier thickness, and a threshold voltage of 1.1–1.3 V for the ridge HEMTs assuming no polarization charge in sidewall channel. The ridge-channel device also exhibits high saturation drain current. The ELO-based ridge-channel opens a new way to achieve normally-off AlGaN/GaN HEMT.

In this letter, we report a quasi-vertical GaN Schottky barrier diode (SBD) fabricated on a hetero-epitaxial layer on silicon with low dislocation density and high carrier mobility. The reduction of dislocation is realized by inserting a thin layer with high density of Ga vacancies to promote the dislocation bending. The dislocation density is $1.6\times 10^8$ cm?2 with a GaN drift layer thickness of $4.5 μ \textm$ . The fabricated prototype GaN SBD delivers a high on/off current ratio of $10^10$ , a high forward current density of 1.6 kA/cm2@3 V, a low specific on-resistance of 1.1 $\textmØmega \cdot \text cm^2$ , and a low ideality factor of 1.23.

In this letter, a distributed network model describing the effects of the border traps and distributed channel resistance on the impedance frequency dispersion of lateral MOS devices is proposed. The proposed model is verified using a gate recessed, normally-off Al2O3/GaN MOSFET structure operating as a MOS diode. The measured frequency-dependent capacitance and conductance curves of the MOS diode over a wide frequency range are found to be in good agreement with the proposed model. According to the intrinsic property of border traps to the ac signal, the proposed model is further modified to get the spatial distribution of border traps. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures.

A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si3N4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si3N4 (30 nm) in AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si3N4/(Al) GaN interface and the effect on threshold voltage (V-TH) instability and dynamic R-ON in the MIS-HEMTs with/without the in-situ Si3N4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) C-V (QSCV), time-offly (TOF) stress/measure, and QS I-D-V-DS methods. It is founded that the in-situ Si3N4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better V-TH stability and lower R-ON, D/R-ON,R-S ratio are observed in devices with the in-situ Si3N4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.

A novel early gate dielectric AIGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) process is reported. With the highquality Si3N4 dielectric by low-pressure chemical vapor deposition and damage free, self-terminating passivation layer etching at the gate area, the MIS-HEMTs on 150-mm Si substrate demonstrate excellent output performance and good uniformity. The interface trap density between the gate insulator and the barrier layer is as low as 2 x 10(12) cm(-2).eV(-1) extracted by the conductance method. The MIS-HEMT fabricated on the wafer delivers an extremely small gate leakage current of 10(-9) mA/mm and a high I-on/I-off ratio of 10(11). The subthreshold swing (SS) is around 80 mV/dec, and the saturated output current density is 750 mA/mm. The dynamic on-resistance increases about 42% at a quiescent drain bias of 600 V. The V-th shift is -0.63 and -0.89 V at a high temperature of 200 degrees C and negative gate-bias stress of -25 V, respectively, indicating a comparable stability with the state-of-the-art MIS-HEMTs. An excellent threshold voltage and SS uniformity (1 - sigma/mu) with the value of 94.5% and 95.2% are achieved on the 150-mm wafer.

Frequency dispersion of the capacitance (C-f) of GaN-based heterostructure are commonly observed at high frequencies. Analytical solutions are derived for frequency dispersion of the heterostructure's capacitance measured on two concentric-circle Schottky contacts, in form of Bessel function, by modeling a distributed network of heterostructure and solving corresponding circular transmission line functions. Solutions reveal C-f is determined by the R-s of 2-D electron gas (2-DEG). So in reverse, the sheet resistance at a certain carrier density can be extracted from the C-f measurement. By fitting experimental C-f data with the model, we obtain a peak mobility of 2044 cm(2)/V.s corresponding to a 2-DEG density of 8.2 x 10(12) cm(-2) and a sheet resistance of 373 Omega/square on an Al0.25Ga0.75N/GaN heterostructure on silicon substrate. The advantage of two Schottky contacts is that they could be implemented by mercury probes with the same geometry, then achieving nondestructive and instant feedback on carrier transport properties and uniformity of as-grown III-V compound semiconductor wafers

In this letter, we demonstrate a recessed-anode Schottky barrier diode (SBD) on a double AlGaN/GaN heterojunction structure. A self-terminated, oxidation/wet etching with low-pressure chemical vapor deposition (LPCVD) Si3N4 mask is applied in the anode recess process. Unlike common plasma-based, dry etching techniques, the etched surface is not subjected to ion bombardment, and the etch depth is precisely controlled. As a result, a high effective channel mobility of 1079 cm2/V . s is maintained in the channel beneath the recess surface. The fabricated devices with a 15-mum anode-to-cathode distance (LAC) are found to exhibit a uniform, low turn-ON voltage (VON) of 0.69 +or- 0.03 V, and a low specific on-resistance (RON,SP) of 2.83 mQ . cm2. The SBDs also show excellent off-state blocking characteristics due to the smooth recess interface together with the assistance of LPCVD grown Si3N4. A breakdown voltage of 1190 V is achieved for the SBDs with 15-mum LAC at a leakage current criteria of 1 muA/mm, and the Baliga's figure-of-merit is 500 MW/cm2.

A gate-recessed normally OFF GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. The LPCVD Si3N4 serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si3N4 as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843 cm(2)/V . s, and low-channel resistance of 0.89 Omega . mm are achieved for a normally OFF channel with L-G = 1.5 mu m. For 3 mu m L-GD, the fabricated devices exhibit a threshold voltage (Vth) of 1.35 V, a maximum drain current of similar to 500 mA/mm, a high ON/OFF current ratio of similar to 1010, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of similar to 10-7 mA/mm up to 10 V. A high Baliga's figure of merit of 1.26 GW/cm(2) is achieved in devices with 10-mu m gate-drain distance.

In this paper, we report the device performance of a high-voltage enhancement-mode (E-mode) GaN MOSHEMT on silicon substrate. Normally off operation is realized by a self-terminated precision gate recess process on an optimized high-electronmobility transistor structure. The GaN MOSHEMT is fully pinched off at zero gate bias, suggesting a ``true'' normally off operation. The threshold voltage is 0.4 V with a drain current density of 1 mu A/mm as the criteria. The device with 15-mu m gate-drain distance and 100-mu m gate width exhibits a maximum drain current of 356 mA/mm at 8-V gate bias. The on/off current ratio of the device is larger than 1010 with a subthreshold slope of 80 mV/dec. The gate leakage current is below 10-7 mA/mm up to 9-V gate bias. The off-state breakdown voltage (BV) is as high as 1528 V (880 V) measured with floating (grounded) silicon substrate at a drain leakage current criterion of 5 mu A/mm. The specific on-resistance (R-ON,R-SP) of the device is 2.79 m Omega.cm(2), and the power figure of merit (BV2/R-ON,R-SP) is 277 MW/cm(2). High-voltage pulsed I-V measurement indicates that the dynamic on-resistance is only 1.6 times the static one with a pulsewidth of 10 mu s at 400-V off-state quiescent drain bias. The high performance of the normally off GaN MOSHEMT is supposed to benefit from the high quality low pressure chemical vapor deposition Si3N4 passivation layer and the advanced E-mode device fabrication process.

The compatibility of Au-free (Ti/Al/Ti/TiN) ohmic contacts in the gate-first double-metal (GFDM) process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) and Schottky barrier diodes (SBDs) on the same 150-mm wafer was investigated and discussed for the first time, including contact pretreatments, Al diffusion in dielectric layers, and vias (contact windows between two metal layers) etching conditions. All of these steps are crucial to ohmic contacts as well as overall AlGaN/GaN device fabrication process. With the optimized ohmic contacts steps, not only an extremely low ohmic contact resistance (RC) value of 1.07 Omega . mm but also an excellent uniformity on the 150-mm wafer was obtained. The performance and uniformity of the MIS-HEMTs and SBDs based on the optimized GFDM process were also discussed.

For devices with a 15 micron anode-to-cathode distance, nearly 1.5 times increase in the blocking (breakdown) voltage (from 692 to 1030 V) has been achieved by replacing the alloyed Ohmic contact at the anode electrode of the conventional MOS gated hybrid-anode lateral field-effect rectifier (CMLFER) with a low barrier Schottky contact. The new Schottky-MOS hybrid-anode lateral field-effect rectifier is found to offer comparable low onset voltage (V-ON of 0.68 +/- 0.13 versus 0.65 +/- 0.11 V for CMLFER) independent of the anode-to- cathode distance. The immunity of the punch through caused by drain induced barrier lowering effect is obtained through the low barrier Schottky contact in anode, which is believed to be responsible for the reduction in the leakage current, and the improvement of rectifier breakdown voltage.

In this letter, a gate recessed normally-off GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate is fabricated using AlN/Si3N4 as the passivation layer. The thin AlN layer serves the dual role of protecting the gate channel region from direct plasma bombardment during the RIE Si3N4 removal and passivating the surface states in the access region. As a result, the effective carrier mobility in the normally-off channel is found to improve from the 568 cm(2)/V . s in conventional Si3N4 passivation process to a high value of 1154 cm(2)/V . s. A saturated output current density of 603 mA/mm and an ON-resistance of 5.3 Omega . mm was obtained for devices with L-G/L-GS/L-GD/W-G = 1.5/1.5/3/20 mu m. Meanwhile, the degradation of dynamic ON-resistance is significantly suppressed due to the effective passivation of surface states by the AlN layer grown by plasma-enhanced atomic layer deposition.

Time-dependent OFF-state leakage behavior of AlGaN/GaN MISHEMTs on silicon substrate is investigated and a novel degradation mechanism is proposed in this paper. Under constant high voltage OFF-state stress, drain leakage current gradually increases with stress time and the behavior is gate bias and temperature-dependent. Consecutive OFF-state breakdown measurement with drain injection technique indicates that the negative shift of threshold voltage (V-th) is responsible for the increase of drain leakage current during stress measurement. It is proposed that the negative shift of V-th is mainly induced by the ionization of uncompensated donor like deep levels near the channel, which are most likely to be located in the 300-nm-thick unintentionally doped GaN layer above the carbon doped buffer layer.