Time-dependent OFF-state leakage behavior of AlGaN/GaN MISHEMTs on silicon substrate is investigated and a novel degradation mechanism is proposed in this paper. Under constant high voltage OFF-state stress, drain leakage current gradually increases with stress time and the behavior is gate bias and temperature-dependent. Consecutive OFF-state breakdown measurement with drain injection technique indicates that the negative shift of threshold voltage (V-th) is responsible for the increase of drain leakage current during stress measurement. It is proposed that the negative shift of V-th is mainly induced by the ionization of uncompensated donor like deep levels near the channel, which are most likely to be located in the 300-nm-thick unintentionally doped GaN layer above the carbon doped buffer layer.

The time-dependent threshold voltage drift induced by fast interface traps in a fully gate-recessed normally-off GaN MOSFET is studied. It is found that the degree and time scale of the shift in threshold voltage are consistent with the density and time constant of interface traps at the MOS interface. The device based on wet etching delivers higher interface quality and threshold voltage stability than that based on dry etching. Nitrogen deficiency and high oxygen coverage are considered to be the origins of the high interface trap density in the MOSFET fabricated by dry etching. (C) 2016 The Japan Society of Applied Physics

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm(2)/V . s was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

The unique nature of built-in electric field induced positive/negative charge pairs of polar semiconductor heterojunction structure has led to a more realistic device model for hexagonal III-nitride HEMT. In this modeling approach, the distribution of charge carriers is dictated by the electrostatic potential profile instead of Femi statistics. The proposed device model is found suitable to explain peculiar properties of GaN HEMT structures, including: (1) Discrepancy in measured conventional linear transmission line model (LTLM) sheet resistance and contactless sheet resistance of GaN HEMT with thin barrier layer. (2) Below bandgap radiation from forward biased Nickel Schottky barrier diode on GaN HEMT structure. (3) GaN HEMT barrier layer doping has negligible effect on transistor channel sheet charge density. (C) 2016 AIP Publishing LLC.

By employing a single AlGaN layer with low Al composition, high quality and uniformity AlGaN/GaN heterostructures have been successfully grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). The heterostructures exhibit a high electron mobility of 2150 cm(2)/Vs with an electron density of 9.3 x 10(12) cm(-2). The sheet resistance is 313 +/- 4 Omega/square with +/- 1.3% variation. The high uniformity is attributed to the reduced wafer bow resulting from the balance of the compressive stress induced and consumed during the growth, and the thermal tensile stress induced during the cooling down process. By a combination of theoretical calculations and in situ wafer curvature measurements, we find that the compressive stress consumed by the dislocation relaxation (similar to 1.2 GPa) is comparable to the value of the thermal tensile stress (similar to 1.4 GPa) and we should pay more attention to it during growth of GaN on Si substrates. Our results demonstrate a promising approach to simplifying the growth processes of GaN-on-Si to reduce the wafer bow and lower the cost while maintaining high material quality.

We present a methodology and the corresponding experimental results to identify the exact location of the traps that induce hot electron trapping in AlGaN/GaN heterostructures grown on Si substrates. The methodology is based on a combination of lateral and vertical electrical stress measurements employing three ohmic terminals on the test sample structure with different GaN buffer designs. By monitoring the evolution of the lateral current during lateral as well as vertical stress application, we investigate the trapping/detrapping behaviors of the hot electrons and identify that the traps correlated with current degradation are in fact located in the GaN buffer layers. The trap activation energies (0.38-0.39 eV and 0.57-0.59 eV) extracted from either lateral or vertical stress measurements are in good agreement with each other, also confirming the identification. By further comparing the trapping behaviors in two samples with different growth conditions of an unintentionally doped GaN layer, we conclude that the traps are most likely in the unintentionally doped GaN layer but of different origins. It is suggested that the 0.38-0.39 eV trap is related to residual carbon incorporation while the 0.57-0.59 eV trap is correlated with native defects or complexes. (C) 2016 AIP Publishing LLC.