In this letter, a distributed network model describing the effects of the border traps and distributed channel resistance on the impedance frequency dispersion of lateral MOS devices is proposed. The proposed model is verified using a gate recessed, normally-off Al2O3/GaN MOSFET structure operating as a MOS diode. The measured frequency-dependent capacitance and conductance curves of the MOS diode over a wide frequency range are found to be in good agreement with the proposed model. According to the intrinsic property of border traps to the ac signal, the proposed model is further modified to get the spatial distribution of border traps. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures.

A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si3N4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si3N4 (30 nm) in AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si3N4/(Al) GaN interface and the effect on threshold voltage (V-TH) instability and dynamic R-ON in the MIS-HEMTs with/without the in-situ Si3N4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) C-V (QSCV), time-offly (TOF) stress/measure, and QS I-D-V-DS methods. It is founded that the in-situ Si3N4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better V-TH stability and lower R-ON, D/R-ON,R-S ratio are observed in devices with the in-situ Si3N4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.