Investigation of the Trap States and V-TH Instability in LPCVD Si3N4/AlGaN/GaN MIS-HEMTs with an In-Situ Si3N4 Interfacial Layer

Citation:

Sun H, Wang M, Yin R, Chen J, Xue S, Luo J, Hao Y, Chen D. Investigation of the Trap States and V-TH Instability in LPCVD Si3N4/AlGaN/GaN MIS-HEMTs with an In-Situ Si3N4 Interfacial Layer. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2019;66:3290-3295.

摘要:

A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si3N4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si3N4 (30 nm) in AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si3N4/(Al) GaN interface and the effect on threshold voltage (V-TH) instability and dynamic R-ON in the MIS-HEMTs with/without the in-situ Si3N4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) C-V (QSCV), time-offly (TOF) stress/measure, and QS I-D-V-DS methods. It is founded that the in-situ Si3N4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better V-TH stability and lower R-ON, D/R-ON,R-S ratio are observed in devices with the in-situ Si3N4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.