This letter reports a GaN high-electron mobility transistor (HEMT) with reduced current collapse using a multicycle combined plasma-free ozone oxidation and wet surface treatment before Si3N4 passivation. The surface oxide and decomposed layers could be effectively removed and a perfect AlGaN surface is obtained after the treatment. Pulsed IV and RF power measurement indicate that the current collapse is greatly suppressed due to the removal of imperfect surface layer and damage free nature, providing an effective surface treatment method to improve the effect of passivation in GaN HEMT.

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level E1 with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while E2 with an activation energy of 0.22 eV is located in the buffer layer.

Threshold voltage drift under gate bias stress was investigated in gate-recessed enhancement mode (E-mode) GaN MOSFET and depletion mode (D-mode) GaN MOS high-electron-mobility transistor (MOSHEMT) with Al2O3 gate dielectric layer. Besides the positive shift of threshold voltage in both devices under positive gate stress, it is also found that positive shift could also exist in E-mode GaN MOSFET under negative gate bias stress, while negative shift is observed in D-mode MOSHEMT. A three-step trapping and detrapping process was observed in the drain current transient of the device after negative gate bias stress. It was suggested that gate electron injection and the following trapping in the ``damaged'' gate recessed GaN channel layer is the dominant mechanism for the positive shift of the threshold voltage under negative gate bias in the enhancement mode GaN MOSFET. (c) 2015 The Japan Society of Applied Physics

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density D-it in MOS structures, Dit in the device with AlN was determined to be in the range of 10(11)-10(12) eV(-1) cm(-2), showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well. (C) 2015 AIP Publishing LLC.

The oxidation mechanism in self-terminating wet etching technique with thermal oxidation of AlGaN layer followed by etching in KOH solution is investigated. Spike-shape remnants of oxidised AlGaN are observed at the initial stage of wet etching in KOH solution, which could be completely etched away after enough etching time. Transmission electron microscope/energy dispersive spectroscopy analysis indicates the existence of crystalline AlGaN inside the remnants. Finally, a possible explanation is given that the oxide channels from AlGaN surface towards AlGaN/GaN interface generated during thermal oxidation are firstly etched away at the initial stage of KOH wet etching, then after enough time these remnants with non-c axis crystal orientation surfaces exposed to KOH solution could be completely etched away leaving GaN layer beneath unaffected, which realises self-terminating etching.

High-temperature transport properties in high-mobility lattice-matched InAlN/GaN heterostructures have been investigated. An interesting hysteresis phenomenon of the two dimensional electron gas (2DEG) density is observed in the temperature-dependent Hall measurements. After high-temperature thermal cycles treatment, the reduction of the 2DEG density is observed, which is more serious in thinner InAlN barrier samples. This reduction can then be recovered by light illumination. We attribute these behaviors to the shallow trap states with energy level above the Fermi level in the GaN buffer layer. The electrons in the 2DEG are thermal-excited when temperature is increased and then trapped by these shallow trap states in the buffer layer, resulting in the reduction and hysteresis phenomenon of their density. Three trap states are observed in the GaN buffer layer and CGa may be one of the candidates responsible for the observed behaviors. Our results provide an alternative approach to assess the quality of InAlN/GaN heterostructures for applications in high-temperature electronic devices. (C) 2015 AIP Publishing LLC.