A novel early gate dielectric AIGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) process is reported. With the highquality Si3N4 dielectric by low-pressure chemical vapor deposition and damage free, self-terminating passivation layer etching at the gate area, the MIS-HEMTs on 150-mm Si substrate demonstrate excellent output performance and good uniformity. The interface trap density between the gate insulator and the barrier layer is as low as 2 x 10(12) cm(-2).eV(-1) extracted by the conductance method. The MIS-HEMT fabricated on the wafer delivers an extremely small gate leakage current of 10(-9) mA/mm and a high I-on/I-off ratio of 10(11). The subthreshold swing (SS) is around 80 mV/dec, and the saturated output current density is 750 mA/mm. The dynamic on-resistance increases about 42% at a quiescent drain bias of 600 V. The V-th shift is -0.63 and -0.89 V at a high temperature of 200 degrees C and negative gate-bias stress of -25 V, respectively, indicating a comparable stability with the state-of-the-art MIS-HEMTs. An excellent threshold voltage and SS uniformity (1 - sigma/mu) with the value of 94.5% and 95.2% are achieved on the 150-mm wafer.

Frequency dispersion of the capacitance (C-f) of GaN-based heterostructure are commonly observed at high frequencies. Analytical solutions are derived for frequency dispersion of the heterostructure's capacitance measured on two concentric-circle Schottky contacts, in form of Bessel function, by modeling a distributed network of heterostructure and solving corresponding circular transmission line functions. Solutions reveal C-f is determined by the R-s of 2-D electron gas (2-DEG). So in reverse, the sheet resistance at a certain carrier density can be extracted from the C-f measurement. By fitting experimental C-f data with the model, we obtain a peak mobility of 2044 cm(2)/V.s corresponding to a 2-DEG density of 8.2 x 10(12) cm(-2) and a sheet resistance of 373 Omega/square on an Al0.25Ga0.75N/GaN heterostructure on silicon substrate. The advantage of two Schottky contacts is that they could be implemented by mercury probes with the same geometry, then achieving nondestructive and instant feedback on carrier transport properties and uniformity of as-grown III-V compound semiconductor wafers

In this letter, we demonstrate a recessed-anode Schottky barrier diode (SBD) on a double AlGaN/GaN heterojunction structure. A self-terminated, oxidation/wet etching with low-pressure chemical vapor deposition (LPCVD) Si3N4 mask is applied in the anode recess process. Unlike common plasma-based, dry etching techniques, the etched surface is not subjected to ion bombardment, and the etch depth is precisely controlled. As a result, a high effective channel mobility of 1079 cm2/V . s is maintained in the channel beneath the recess surface. The fabricated devices with a 15-mum anode-to-cathode distance (LAC) are found to exhibit a uniform, low turn-ON voltage (VON) of 0.69 +or- 0.03 V, and a low specific on-resistance (RON,SP) of 2.83 mQ . cm2. The SBDs also show excellent off-state blocking characteristics due to the smooth recess interface together with the assistance of LPCVD grown Si3N4. A breakdown voltage of 1190 V is achieved for the SBDs with 15-mum LAC at a leakage current criteria of 1 muA/mm, and the Baliga's figure-of-merit is 500 MW/cm2.

A gate-recessed normally OFF GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. The LPCVD Si3N4 serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si3N4 as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843 cm(2)/V . s, and low-channel resistance of 0.89 Omega . mm are achieved for a normally OFF channel with L-G = 1.5 mu m. For 3 mu m L-GD, the fabricated devices exhibit a threshold voltage (Vth) of 1.35 V, a maximum drain current of similar to 500 mA/mm, a high ON/OFF current ratio of similar to 1010, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of similar to 10-7 mA/mm up to 10 V. A high Baliga's figure of merit of 1.26 GW/cm(2) is achieved in devices with 10-mu m gate-drain distance.

In this paper, we report the device performance of a high-voltage enhancement-mode (E-mode) GaN MOSHEMT on silicon substrate. Normally off operation is realized by a self-terminated precision gate recess process on an optimized high-electronmobility transistor structure. The GaN MOSHEMT is fully pinched off at zero gate bias, suggesting a ``true'' normally off operation. The threshold voltage is 0.4 V with a drain current density of 1 mu A/mm as the criteria. The device with 15-mu m gate-drain distance and 100-mu m gate width exhibits a maximum drain current of 356 mA/mm at 8-V gate bias. The on/off current ratio of the device is larger than 1010 with a subthreshold slope of 80 mV/dec. The gate leakage current is below 10-7 mA/mm up to 9-V gate bias. The off-state breakdown voltage (BV) is as high as 1528 V (880 V) measured with floating (grounded) silicon substrate at a drain leakage current criterion of 5 mu A/mm. The specific on-resistance (R-ON,R-SP) of the device is 2.79 m Omega.cm(2), and the power figure of merit (BV2/R-ON,R-SP) is 277 MW/cm(2). High-voltage pulsed I-V measurement indicates that the dynamic on-resistance is only 1.6 times the static one with a pulsewidth of 10 mu s at 400-V off-state quiescent drain bias. The high performance of the normally off GaN MOSHEMT is supposed to benefit from the high quality low pressure chemical vapor deposition Si3N4 passivation layer and the advanced E-mode device fabrication process.

The compatibility of Au-free (Ti/Al/Ti/TiN) ohmic contacts in the gate-first double-metal (GFDM) process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) and Schottky barrier diodes (SBDs) on the same 150-mm wafer was investigated and discussed for the first time, including contact pretreatments, Al diffusion in dielectric layers, and vias (contact windows between two metal layers) etching conditions. All of these steps are crucial to ohmic contacts as well as overall AlGaN/GaN device fabrication process. With the optimized ohmic contacts steps, not only an extremely low ohmic contact resistance (RC) value of 1.07 Omega . mm but also an excellent uniformity on the 150-mm wafer was obtained. The performance and uniformity of the MIS-HEMTs and SBDs based on the optimized GFDM process were also discussed.