Enhancement-mode (E-mode) p-channel field-effect transistors (p-FETs) remain challenging for GaN complementary logic (CL) technology due to their unstable threshold voltage (Vth), low current density, and large on-resistance (RON) at 6 V CL-compatible operation. In this work, we demonstrate a high-performance E-mode GaN p-FET with a p-NiO/p-GaN heterojunction gate. Notably, the suppressed Vth shift and improved channel conductivity were simultaneously achieved in the E-mode channel. The improvement is primarily due to the type-II band alignment at the p-NiO/p-GaN interface. This structure reduces band overlap, resulting in a low interface trap density (DT) of 3.29–5.71 × 1010 cm−2 eV−1 as measured by the sub-bandgap photo-assisted capacitance–voltage method. The fabricated device with LG/LGS/LGD = 1.5/3/3 μm exhibits a Vth of −0.6 V with a minimal hysteresis of 0.02 V and maximum shift of 0.04 V under stress, a ID of 5.5 mA/mm, a RON of 0.47 k Ω mm, and a transconductance (gm) of 1.8 mS/mm for 6 V CL-compatible operation.

In this paper, we reported the mechanism of a bimodal Weibull distribution for TDDB of gate dielectric in GaN MISHEMT. It is shown that the properties of traps in the dielectric layer would have a great influence on the long time reliability and life time prediction process. 

In this study, the physical properties of F ion-implanted GaN were thoroughly studied, and the related electric-field modulation mechanisms in ion-implanted edge termination were revealed. Transmission electron microscopy results indicate that the ion-implanted region maintains a single-crystal structure even with the implantation of high-energy F ions, indicating that the high resistivity of the edge termination region is not induced by amorphization. Alternately, ion implantation-induced deep levels could compensate the electrons and lead to a highly resistive layer. In addition to the bulk effect, the direct bombardment of high-energy F ions resulted in a rough and nitrogen-deficient surface, which was confirmed via atomic force microscopy (AFM) and X-ray photoelectron spectroscopy. The implanted surface with a large density of nitrogen vacancies can accommodate electrons, and it is more conductive than the bulk in the implanted region, which is validated via spreading resistance profiling and conductive AFM measurements. Under reverse bias, the implanted surface can spread the potential in the lateral direction, whereas the acceptor traps capture electrons acting as space charges, shifting the peak electric field into the bulk region in the vertical direction. As a result, the Schottky barrier diode terminated with high-energy F ion-implanted regions exhibits a breakdown voltage of over 1.2 kV.

A ridge-channel AlGaN/GaN high-electron mobility transistor (HEMT) utilizing selective-area growth and epitaxial lateral overgrowth (ELO) technique is proposed in this work to achieve high-performance normally-off devices. It has a c-plane platform for the source and the drain contacts, and sidewalls of lattice plane for the gate contact. The sidewalls have characteristics of weak polarization and thin barrier, which are advantageous for realizing normally-off operation. Two ridge HEMTs with triangular and trapezoid channel are designed. Theoretical simulation demonstrates a threshold voltage of 0.03 V for the sidewall channel with reduced polarization and barrier thickness, and a threshold voltage of 1.1–1.3 V for the ridge HEMTs assuming no polarization charge in sidewall channel. The ridge-channel device also exhibits high saturation drain current. The ELO-based ridge-channel opens a new way to achieve normally-off AlGaN/GaN HEMT.

In this letter, we report a quasi-vertical GaN Schottky barrier diode (SBD) fabricated on a hetero-epitaxial layer on silicon with low dislocation density and high carrier mobility. The reduction of dislocation is realized by inserting a thin layer with high density of Ga vacancies to promote the dislocation bending. The dislocation density is $1.6\times 10^8$ cm?2 with a GaN drift layer thickness of $4.5 μ \textm$ . The fabricated prototype GaN SBD delivers a high on/off current ratio of $10^10$ , a high forward current density of 1.6 kA/cm2@3 V, a low specific on-resistance of 1.1 $\textmØmega \cdot \text cm^2$ , and a low ideality factor of 1.23.

In this letter, a distributed network model describing the effects of the border traps and distributed channel resistance on the impedance frequency dispersion of lateral MOS devices is proposed. The proposed model is verified using a gate recessed, normally-off Al2O3/GaN MOSFET structure operating as a MOS diode. The measured frequency-dependent capacitance and conductance curves of the MOS diode over a wide frequency range are found to be in good agreement with the proposed model. According to the intrinsic property of border traps to the ac signal, the proposed model is further modified to get the spatial distribution of border traps. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures.