<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Hui Sun</style></author><author><style face="normal" font="default" size="100%">Wang, Maojun</style></author><author><style face="normal" font="default" size="100%">Yin, Ruiyuan</style></author><author><style face="normal" font="default" size="100%">Jianguo Chen</style></author><author><style face="normal" font="default" size="100%">Xue, Shuai</style></author><author><style face="normal" font="default" size="100%">Luo, Jiansheng</style></author><author><style face="normal" font="default" size="100%">Hao, Yilong</style></author><author><style face="normal" font="default" size="100%">Dongmin Chen</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Investigation of the Trap States and V-TH Instability in LPCVD Si3N4/AlGaN/GaN MIS-HEMTs with an In-Situ Si3N4 Interfacial Layer</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE TRANSACTIONS ON ELECTRON DEVICES</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">AlGaN/GaN</style></keyword><keyword><style  face="normal" font="default" size="100%">in-situ Si3N4</style></keyword><keyword><style  face="normal" font="default" size="100%">low-pressure chemical vapor deposition (LPCVD) Si3N4</style></keyword><keyword><style  face="normal" font="default" size="100%">metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT)</style></keyword><keyword><style  face="normal" font="default" size="100%">quasi-static (QS) C-V</style></keyword><keyword><style  face="normal" font="default" size="100%">trap states</style></keyword><keyword><style  face="normal" font="default" size="100%">V-TH instability</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2019</style></year><pub-dates><date><style  face="normal" font="default" size="100%">AUG</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">8</style></number><publisher><style face="normal" font="default" size="100%">IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC</style></publisher><pub-location><style face="normal" font="default" size="100%">445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA</style></pub-location><volume><style face="normal" font="default" size="100%">66</style></volume><pages><style face="normal" font="default" size="100%">3290-3295</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si3N4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si3N4 (30 nm) in AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si3N4/(Al) GaN interface and the effect on threshold voltage (V-TH) instability and dynamic R-ON in the MIS-HEMTs with/without the in-situ Si3N4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) C-V (QSCV), time-offly (TOF) stress/measure, and QS I-D-V-DS methods. It is founded that the in-situ Si3N4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better V-TH stability and lower R-ON, D/R-ON,R-S ratio are observed in devices with the in-situ Si3N4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.</style></abstract><work-type><style face="normal" font="default" size="100%">Article</style></work-type></record></records></xml>