The time-dependent threshold voltage drift induced by fast interface traps in a fully gate-recessed normally-off GaN MOSFET is studied. It is found that the degree and time scale of the shift in threshold voltage are consistent with the density and time constant of interface traps at the MOS interface. The device based on wet etching delivers higher interface quality and threshold voltage stability than that based on dry etching. Nitrogen deficiency and high oxygen coverage are considered to be the origins of the high interface trap density in the MOSFET fabricated by dry etching. (C) 2016 The Japan Society of Applied Physics

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm(2)/V . s was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

The unique nature of built-in electric field induced positive/negative charge pairs of polar semiconductor heterojunction structure has led to a more realistic device model for hexagonal III-nitride HEMT. In this modeling approach, the distribution of charge carriers is dictated by the electrostatic potential profile instead of Femi statistics. The proposed device model is found suitable to explain peculiar properties of GaN HEMT structures, including: (1) Discrepancy in measured conventional linear transmission line model (LTLM) sheet resistance and contactless sheet resistance of GaN HEMT with thin barrier layer. (2) Below bandgap radiation from forward biased Nickel Schottky barrier diode on GaN HEMT structure. (3) GaN HEMT barrier layer doping has negligible effect on transistor channel sheet charge density. (C) 2016 AIP Publishing LLC.

By employing a single AlGaN layer with low Al composition, high quality and uniformity AlGaN/GaN heterostructures have been successfully grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). The heterostructures exhibit a high electron mobility of 2150 cm(2)/Vs with an electron density of 9.3 x 10(12) cm(-2). The sheet resistance is 313 +/- 4 Omega/square with +/- 1.3% variation. The high uniformity is attributed to the reduced wafer bow resulting from the balance of the compressive stress induced and consumed during the growth, and the thermal tensile stress induced during the cooling down process. By a combination of theoretical calculations and in situ wafer curvature measurements, we find that the compressive stress consumed by the dislocation relaxation (similar to 1.2 GPa) is comparable to the value of the thermal tensile stress (similar to 1.4 GPa) and we should pay more attention to it during growth of GaN on Si substrates. Our results demonstrate a promising approach to simplifying the growth processes of GaN-on-Si to reduce the wafer bow and lower the cost while maintaining high material quality.

We present a methodology and the corresponding experimental results to identify the exact location of the traps that induce hot electron trapping in AlGaN/GaN heterostructures grown on Si substrates. The methodology is based on a combination of lateral and vertical electrical stress measurements employing three ohmic terminals on the test sample structure with different GaN buffer designs. By monitoring the evolution of the lateral current during lateral as well as vertical stress application, we investigate the trapping/detrapping behaviors of the hot electrons and identify that the traps correlated with current degradation are in fact located in the GaN buffer layers. The trap activation energies (0.38-0.39 eV and 0.57-0.59 eV) extracted from either lateral or vertical stress measurements are in good agreement with each other, also confirming the identification. By further comparing the trapping behaviors in two samples with different growth conditions of an unintentionally doped GaN layer, we conclude that the traps are most likely in the unintentionally doped GaN layer but of different origins. It is suggested that the 0.38-0.39 eV trap is related to residual carbon incorporation while the 0.57-0.59 eV trap is correlated with native defects or complexes. (C) 2016 AIP Publishing LLC.

This letter reports a GaN high-electron mobility transistor (HEMT) with reduced current collapse using a multicycle combined plasma-free ozone oxidation and wet surface treatment before Si3N4 passivation. The surface oxide and decomposed layers could be effectively removed and a perfect AlGaN surface is obtained after the treatment. Pulsed IV and RF power measurement indicate that the current collapse is greatly suppressed due to the removal of imperfect surface layer and damage free nature, providing an effective surface treatment method to improve the effect of passivation in GaN HEMT.

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level E1 with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while E2 with an activation energy of 0.22 eV is located in the buffer layer.

Threshold voltage drift under gate bias stress was investigated in gate-recessed enhancement mode (E-mode) GaN MOSFET and depletion mode (D-mode) GaN MOS high-electron-mobility transistor (MOSHEMT) with Al2O3 gate dielectric layer. Besides the positive shift of threshold voltage in both devices under positive gate stress, it is also found that positive shift could also exist in E-mode GaN MOSFET under negative gate bias stress, while negative shift is observed in D-mode MOSHEMT. A three-step trapping and detrapping process was observed in the drain current transient of the device after negative gate bias stress. It was suggested that gate electron injection and the following trapping in the ``damaged'' gate recessed GaN channel layer is the dominant mechanism for the positive shift of the threshold voltage under negative gate bias in the enhancement mode GaN MOSFET. (c) 2015 The Japan Society of Applied Physics

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density D-it in MOS structures, Dit in the device with AlN was determined to be in the range of 10(11)-10(12) eV(-1) cm(-2), showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well. (C) 2015 AIP Publishing LLC.

The oxidation mechanism in self-terminating wet etching technique with thermal oxidation of AlGaN layer followed by etching in KOH solution is investigated. Spike-shape remnants of oxidised AlGaN are observed at the initial stage of wet etching in KOH solution, which could be completely etched away after enough etching time. Transmission electron microscope/energy dispersive spectroscopy analysis indicates the existence of crystalline AlGaN inside the remnants. Finally, a possible explanation is given that the oxide channels from AlGaN surface towards AlGaN/GaN interface generated during thermal oxidation are firstly etched away at the initial stage of KOH wet etching, then after enough time these remnants with non-c axis crystal orientation surfaces exposed to KOH solution could be completely etched away leaving GaN layer beneath unaffected, which realises self-terminating etching.

High-temperature transport properties in high-mobility lattice-matched InAlN/GaN heterostructures have been investigated. An interesting hysteresis phenomenon of the two dimensional electron gas (2DEG) density is observed in the temperature-dependent Hall measurements. After high-temperature thermal cycles treatment, the reduction of the 2DEG density is observed, which is more serious in thinner InAlN barrier samples. This reduction can then be recovered by light illumination. We attribute these behaviors to the shallow trap states with energy level above the Fermi level in the GaN buffer layer. The electrons in the 2DEG are thermal-excited when temperature is increased and then trapped by these shallow trap states in the buffer layer, resulting in the reduction and hysteresis phenomenon of their density. Three trap states are observed in the GaN buffer layer and CGa may be one of the candidates responsible for the observed behaviors. Our results provide an alternative approach to assess the quality of InAlN/GaN heterostructures for applications in high-temperature electronic devices. (C) 2015 AIP Publishing LLC.

In this paper, we report the device performance of a high-voltage normally off Al2O3/GaN MOSFET on the Si substrate. Normally off operation is obtained by multiple cycles of O-2 plasma oxidation and wet oxide-removal gate recess process. The recessed normally off GaN MOSFET with 3 mu m gate-drain distance exhibits a maximum drain current of 585 mA/mm at 9 V gate bias. The threshold voltage of the MOSFET is 2.8 V with a standard derivation of 0.2 V on the sample with an area of 2 x 2 cm(2). The gate leakage current is below 10(-6) mA/mm during the whole gate swing up to 9 V and the I-ON/I-OFF ratio is larger than 10(9), indicating the good quality of Al2O3 gate insulator. The MOSFET with 10 mu m gate-drain distance shows a three terminal OFF-state breakdown voltage (BV) of 967 V at zero gate-source bias with a drain leakage current criterion of 1 mu A/mm. The specific ON-resistance (R-ON,R- SP) of the device is 1.6 m Omega . cm(2) and the power figure of merit (BV2/R-ON,R- SP) is 584 MW/cm(2).

High temperature characteristics of GaN-based inverter is presented from room temperature (RT) to 300 degrees C, which is integrated with enhancement-mode MOSFET and depletion-mode HEMT. At 300 degrees C, the fabricated inverter operates properly at a supply voltage (V-DD) of 7 V with 6.5 V for logic voltage swing, 3.3 V for threshold voltage (V-TH), 2.4 V for logic-low noise margin (NML), and 3.4 V for logic-high noise margin (NMH). Meanwhile, the inverter exhibits small variations from RT to 300 degrees C in terms of logic voltage swing, V-TH, NML, and NMH with the maximum relative variations of 2.2%, 5.7%, 12.9%, and 4.9% in such temperature range, respectively.

A self-terminating gate recess wet etching technique with thermal oxidation of the AlGaN/GaN layer followed by etching in potassium hydroxide (KOH) solution was recently proposed by the present authors for normally-off AlGaN/GaN metal-oxide semiconductor field effect transistors (MOSFETs). In this present reported work, the oxidation process inside the AlGaN/GaN heterostructure involved in this technique was analysed using several material characterisation methods. The measurement results show that the concentration and depth of the O element distribution increase with increased thermal oxidation temperature. It is worth noting that after 650 degrees C oxidation almost no O element could be found in the GaN layer and the O element mainly locates in the AlGaN layer with an obvious correlation between the distribution of Al and O elements, where the Al(Ga)-oxide was detected by X-ray photoelectron spectroscopy, which could be etched by 70 degrees C KOH. Thus, self-terminating wet etching on the AlGaN/GaN material is achieved.

Based on our proposed self-terminating gate recess etching technique, normally-off recess-gated AlGaN/GaN MOSFET has been demonstrated with a novel method using GaN cap layer (CL) as recess mask, which, as a result, simplifies the device fabrication process and lowers the fabrication cost. The GaN CL is capable of acting as an effective recess mask for the gate recess process, which includes a thermal oxidation for 45 min at 650 degrees C followed by 4-min etching in potassium hydroxide (KOH) at 70 degrees C. After gate recess process, no obvious change is observed in terms of the surface morphology of the GaN CL, the contact resistance of the Ohmic contact formed directly on the GaN CL as well as the sheet resistance of the two-dimensional electron gas (2-DEG) channel layer under the GaN CL. The fabricated device exhibits a threshold voltage (V-th) as high as 5 V, a maximum drain current (I-dmax) of similar to 200 mA/mm, a high ON/OFF current ratio of similar to 10(10) together with a low forward gate leakage current of similar to 10(-5) mA/mm. Meanwhile, the OFF-state breakdown voltage (V-br) of the device with gate-drain distance of 6 mu m is 450 V.

Postgate annealing (PGA) in N-2/O-2 atmosphere at 300 degrees C for various annealing time is performed on enhancement mode AlGaN/GaN MOSFET fabricated using a self-terminating gate recess etching technique. After 45-min annealing, the device OFF-state leakage current decreases by more than two orders of magnitude and thus a low OFF-state leakage current of similar to 10(-13) A/mm is obtained at room temperature, resulting in an excellent ON/OFF current ratio of similar to 10(12). At 250 degrees C, the device still exhibits a low OFF-state leakage current of similar to 10(-9) A/mm and high ON/OFF current ratio of similar to 10(8). Meanwhile, a strong correlation between the OFF-state leakage current and mesa isolation current is observed as we change the annealing time: 1) the lower the mesa isolation current and 2) the lower the OFF-state leakage current and thus the higher the ON/OFF current ratio. It is the suppression of the mesa isolation current owing to the passivation of atomic layer deposition Al2O3 that leads to the improvement of the OFF-state leakage current and ON/OFF current ratio after PGA. Besides, the device shows no obvious change in terms of its threshold voltage and maximum drain current after PGA.

In this letter, we investigated the behaviors of surface-and buffer-induced current collapse in AlGaN/GaN high-electron mobility transistors (HEMTs) using a soft-switched pulsed I-V measurement with different quiescent bias points. It is found that the surface-and buffer-related current collapse have different relationship with the gate and drain biases (V-GS0, V-DS0) during quiescent bias stress. The surface-induced current collapse in devices without passivation monotonically increases with the negative V-GS0, suggesting that an electron injection to the surface from gate leakage is the dominant mechanism and the Si3N4 passivation could effectively eliminate such current collapse. The buffer-induced current collapse in devices with intentionally carbon-doped buffer layer exhibits a different relationship with V-GS0 after surface passivation. The buffer-related current collapse shows a bell-shaped behavior with V-GS0, suggesting that a hot electron trapping in the buffer is the dominant mechanism. The soft-switched pulsed I-V measurement provides an effective method to distinguish between the surface-and buffer-related current collapse in group III-nitride HEMTs.

A novel simple approach to extract parasitic source and drain resistances of high electron mobility transistors (HEMT) is presented. This method could obtain the parasitic resistances by determining the portion of channel resistance involved in the measured end-resistance based on the identification of the channel position corresponding to the measured floating-gate voltage with the floating-gate, drain-and source-current-injection configurations on a single device. The technique is demonstrated on AlGaN/GaN HEMTs. It is found that the ratio of the channel resistance involving in the end-resistance to the total channel resistance approaches to a constant independent on the gate length, which could simplify the practical application of this novel method. The experimental results show that the source and drain resistances extracted by this method coincide with series resistance extracted by traditional Transmission Line Model (TLM) measurement. (C) 2014 Elsevier Ltd. All rights reserved.

We report a high-performance normally-off Al2O3/AlN/GaN MOS-channel-high electron mobility transistor (MOSC-HEMT) featuring a monocrystalline AlN interfacial layer inserted between the amorphous Al2O3 gate dielectric and the GaN channel. The AlN interfacial layer effectively blocks oxygen from the GaN surface and prevents the formation of detrimental Ga-O bonds. Frequency-dispersion in C-V characteristics and threshold voltage hysteresis are effectively suppressed, owing to improved interface quality. The new MOSC-HEMTs exhibit a maximum drain current of 660 mA/mm, a field-effect mobility of 165 cm(2)/V . s, a high ON/OFF drain current ratio of similar to 10(10), and low dynamic ON-resistance degradation.