A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si3N4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si3N4 (30 nm) in AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si3N4/(Al) GaN interface and the effect on threshold voltage (V-TH) instability and dynamic R-ON in the MIS-HEMTs with/without the in-situ Si3N4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) C-V (QSCV), time-offly (TOF) stress/measure, and QS I-D-V-DS methods. It is founded that the in-situ Si3N4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better V-TH stability and lower R-ON, D/R-ON,R-S ratio are observed in devices with the in-situ Si3N4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.

A novel early gate dielectric AIGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) process is reported. With the highquality Si3N4 dielectric by low-pressure chemical vapor deposition and damage free, self-terminating passivation layer etching at the gate area, the MIS-HEMTs on 150-mm Si substrate demonstrate excellent output performance and good uniformity. The interface trap density between the gate insulator and the barrier layer is as low as 2 x 10(12) cm(-2).eV(-1) extracted by the conductance method. The MIS-HEMT fabricated on the wafer delivers an extremely small gate leakage current of 10(-9) mA/mm and a high I-on/I-off ratio of 10(11). The subthreshold swing (SS) is around 80 mV/dec, and the saturated output current density is 750 mA/mm. The dynamic on-resistance increases about 42% at a quiescent drain bias of 600 V. The V-th shift is -0.63 and -0.89 V at a high temperature of 200 degrees C and negative gate-bias stress of -25 V, respectively, indicating a comparable stability with the state-of-the-art MIS-HEMTs. An excellent threshold voltage and SS uniformity (1 - sigma/mu) with the value of 94.5% and 95.2% are achieved on the 150-mm wafer.

Frequency dispersion of the capacitance (C-f) of GaN-based heterostructure are commonly observed at high frequencies. Analytical solutions are derived for frequency dispersion of the heterostructure's capacitance measured on two concentric-circle Schottky contacts, in form of Bessel function, by modeling a distributed network of heterostructure and solving corresponding circular transmission line functions. Solutions reveal C-f is determined by the R-s of 2-D electron gas (2-DEG). So in reverse, the sheet resistance at a certain carrier density can be extracted from the C-f measurement. By fitting experimental C-f data with the model, we obtain a peak mobility of 2044 cm(2)/V.s corresponding to a 2-DEG density of 8.2 x 10(12) cm(-2) and a sheet resistance of 373 Omega/square on an Al0.25Ga0.75N/GaN heterostructure on silicon substrate. The advantage of two Schottky contacts is that they could be implemented by mercury probes with the same geometry, then achieving nondestructive and instant feedback on carrier transport properties and uniformity of as-grown III-V compound semiconductor wafers

In this letter, we demonstrate a recessed-anode Schottky barrier diode (SBD) on a double AlGaN/GaN heterojunction structure. A self-terminated, oxidation/wet etching with low-pressure chemical vapor deposition (LPCVD) Si3N4 mask is applied in the anode recess process. Unlike common plasma-based, dry etching techniques, the etched surface is not subjected to ion bombardment, and the etch depth is precisely controlled. As a result, a high effective channel mobility of 1079 cm2/V . s is maintained in the channel beneath the recess surface. The fabricated devices with a 15-mum anode-to-cathode distance (LAC) are found to exhibit a uniform, low turn-ON voltage (VON) of 0.69 +or- 0.03 V, and a low specific on-resistance (RON,SP) of 2.83 mQ . cm2. The SBDs also show excellent off-state blocking characteristics due to the smooth recess interface together with the assistance of LPCVD grown Si3N4. A breakdown voltage of 1190 V is achieved for the SBDs with 15-mum LAC at a leakage current criteria of 1 muA/mm, and the Baliga's figure-of-merit is 500 MW/cm2.

A gate-recessed normally OFF GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. The LPCVD Si3N4 serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si3N4 as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843 cm(2)/V . s, and low-channel resistance of 0.89 Omega . mm are achieved for a normally OFF channel with L-G = 1.5 mu m. For 3 mu m L-GD, the fabricated devices exhibit a threshold voltage (Vth) of 1.35 V, a maximum drain current of similar to 500 mA/mm, a high ON/OFF current ratio of similar to 1010, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of similar to 10-7 mA/mm up to 10 V. A high Baliga's figure of merit of 1.26 GW/cm(2) is achieved in devices with 10-mu m gate-drain distance.

In this paper, we report the device performance of a high-voltage enhancement-mode (E-mode) GaN MOSHEMT on silicon substrate. Normally off operation is realized by a self-terminated precision gate recess process on an optimized high-electronmobility transistor structure. The GaN MOSHEMT is fully pinched off at zero gate bias, suggesting a ``true'' normally off operation. The threshold voltage is 0.4 V with a drain current density of 1 mu A/mm as the criteria. The device with 15-mu m gate-drain distance and 100-mu m gate width exhibits a maximum drain current of 356 mA/mm at 8-V gate bias. The on/off current ratio of the device is larger than 1010 with a subthreshold slope of 80 mV/dec. The gate leakage current is below 10-7 mA/mm up to 9-V gate bias. The off-state breakdown voltage (BV) is as high as 1528 V (880 V) measured with floating (grounded) silicon substrate at a drain leakage current criterion of 5 mu A/mm. The specific on-resistance (R-ON,R-SP) of the device is 2.79 m Omega.cm(2), and the power figure of merit (BV2/R-ON,R-SP) is 277 MW/cm(2). High-voltage pulsed I-V measurement indicates that the dynamic on-resistance is only 1.6 times the static one with a pulsewidth of 10 mu s at 400-V off-state quiescent drain bias. The high performance of the normally off GaN MOSHEMT is supposed to benefit from the high quality low pressure chemical vapor deposition Si3N4 passivation layer and the advanced E-mode device fabrication process.

The compatibility of Au-free (Ti/Al/Ti/TiN) ohmic contacts in the gate-first double-metal (GFDM) process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) and Schottky barrier diodes (SBDs) on the same 150-mm wafer was investigated and discussed for the first time, including contact pretreatments, Al diffusion in dielectric layers, and vias (contact windows between two metal layers) etching conditions. All of these steps are crucial to ohmic contacts as well as overall AlGaN/GaN device fabrication process. With the optimized ohmic contacts steps, not only an extremely low ohmic contact resistance (RC) value of 1.07 Omega . mm but also an excellent uniformity on the 150-mm wafer was obtained. The performance and uniformity of the MIS-HEMTs and SBDs based on the optimized GFDM process were also discussed.

For devices with a 15 micron anode-to-cathode distance, nearly 1.5 times increase in the blocking (breakdown) voltage (from 692 to 1030 V) has been achieved by replacing the alloyed Ohmic contact at the anode electrode of the conventional MOS gated hybrid-anode lateral field-effect rectifier (CMLFER) with a low barrier Schottky contact. The new Schottky-MOS hybrid-anode lateral field-effect rectifier is found to offer comparable low onset voltage (V-ON of 0.68 +/- 0.13 versus 0.65 +/- 0.11 V for CMLFER) independent of the anode-to- cathode distance. The immunity of the punch through caused by drain induced barrier lowering effect is obtained through the low barrier Schottky contact in anode, which is believed to be responsible for the reduction in the leakage current, and the improvement of rectifier breakdown voltage.

In this letter, a gate recessed normally-off GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate is fabricated using AlN/Si3N4 as the passivation layer. The thin AlN layer serves the dual role of protecting the gate channel region from direct plasma bombardment during the RIE Si3N4 removal and passivating the surface states in the access region. As a result, the effective carrier mobility in the normally-off channel is found to improve from the 568 cm(2)/V . s in conventional Si3N4 passivation process to a high value of 1154 cm(2)/V . s. A saturated output current density of 603 mA/mm and an ON-resistance of 5.3 Omega . mm was obtained for devices with L-G/L-GS/L-GD/W-G = 1.5/1.5/3/20 mu m. Meanwhile, the degradation of dynamic ON-resistance is significantly suppressed due to the effective passivation of surface states by the AlN layer grown by plasma-enhanced atomic layer deposition.

Time-dependent OFF-state leakage behavior of AlGaN/GaN MISHEMTs on silicon substrate is investigated and a novel degradation mechanism is proposed in this paper. Under constant high voltage OFF-state stress, drain leakage current gradually increases with stress time and the behavior is gate bias and temperature-dependent. Consecutive OFF-state breakdown measurement with drain injection technique indicates that the negative shift of threshold voltage (V-th) is responsible for the increase of drain leakage current during stress measurement. It is proposed that the negative shift of V-th is mainly induced by the ionization of uncompensated donor like deep levels near the channel, which are most likely to be located in the 300-nm-thick unintentionally doped GaN layer above the carbon doped buffer layer.

The time-dependent threshold voltage drift induced by fast interface traps in a fully gate-recessed normally-off GaN MOSFET is studied. It is found that the degree and time scale of the shift in threshold voltage are consistent with the density and time constant of interface traps at the MOS interface. The device based on wet etching delivers higher interface quality and threshold voltage stability than that based on dry etching. Nitrogen deficiency and high oxygen coverage are considered to be the origins of the high interface trap density in the MOSFET fabricated by dry etching. (C) 2016 The Japan Society of Applied Physics

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm(2)/V . s was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

The unique nature of built-in electric field induced positive/negative charge pairs of polar semiconductor heterojunction structure has led to a more realistic device model for hexagonal III-nitride HEMT. In this modeling approach, the distribution of charge carriers is dictated by the electrostatic potential profile instead of Femi statistics. The proposed device model is found suitable to explain peculiar properties of GaN HEMT structures, including: (1) Discrepancy in measured conventional linear transmission line model (LTLM) sheet resistance and contactless sheet resistance of GaN HEMT with thin barrier layer. (2) Below bandgap radiation from forward biased Nickel Schottky barrier diode on GaN HEMT structure. (3) GaN HEMT barrier layer doping has negligible effect on transistor channel sheet charge density. (C) 2016 AIP Publishing LLC.

By employing a single AlGaN layer with low Al composition, high quality and uniformity AlGaN/GaN heterostructures have been successfully grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). The heterostructures exhibit a high electron mobility of 2150 cm(2)/Vs with an electron density of 9.3 x 10(12) cm(-2). The sheet resistance is 313 +/- 4 Omega/square with +/- 1.3% variation. The high uniformity is attributed to the reduced wafer bow resulting from the balance of the compressive stress induced and consumed during the growth, and the thermal tensile stress induced during the cooling down process. By a combination of theoretical calculations and in situ wafer curvature measurements, we find that the compressive stress consumed by the dislocation relaxation (similar to 1.2 GPa) is comparable to the value of the thermal tensile stress (similar to 1.4 GPa) and we should pay more attention to it during growth of GaN on Si substrates. Our results demonstrate a promising approach to simplifying the growth processes of GaN-on-Si to reduce the wafer bow and lower the cost while maintaining high material quality.

We present a methodology and the corresponding experimental results to identify the exact location of the traps that induce hot electron trapping in AlGaN/GaN heterostructures grown on Si substrates. The methodology is based on a combination of lateral and vertical electrical stress measurements employing three ohmic terminals on the test sample structure with different GaN buffer designs. By monitoring the evolution of the lateral current during lateral as well as vertical stress application, we investigate the trapping/detrapping behaviors of the hot electrons and identify that the traps correlated with current degradation are in fact located in the GaN buffer layers. The trap activation energies (0.38-0.39 eV and 0.57-0.59 eV) extracted from either lateral or vertical stress measurements are in good agreement with each other, also confirming the identification. By further comparing the trapping behaviors in two samples with different growth conditions of an unintentionally doped GaN layer, we conclude that the traps are most likely in the unintentionally doped GaN layer but of different origins. It is suggested that the 0.38-0.39 eV trap is related to residual carbon incorporation while the 0.57-0.59 eV trap is correlated with native defects or complexes. (C) 2016 AIP Publishing LLC.

This letter reports a GaN high-electron mobility transistor (HEMT) with reduced current collapse using a multicycle combined plasma-free ozone oxidation and wet surface treatment before Si3N4 passivation. The surface oxide and decomposed layers could be effectively removed and a perfect AlGaN surface is obtained after the treatment. Pulsed IV and RF power measurement indicate that the current collapse is greatly suppressed due to the removal of imperfect surface layer and damage free nature, providing an effective surface treatment method to improve the effect of passivation in GaN HEMT.

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level E1 with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while E2 with an activation energy of 0.22 eV is located in the buffer layer.

Threshold voltage drift under gate bias stress was investigated in gate-recessed enhancement mode (E-mode) GaN MOSFET and depletion mode (D-mode) GaN MOS high-electron-mobility transistor (MOSHEMT) with Al2O3 gate dielectric layer. Besides the positive shift of threshold voltage in both devices under positive gate stress, it is also found that positive shift could also exist in E-mode GaN MOSFET under negative gate bias stress, while negative shift is observed in D-mode MOSHEMT. A three-step trapping and detrapping process was observed in the drain current transient of the device after negative gate bias stress. It was suggested that gate electron injection and the following trapping in the ``damaged'' gate recessed GaN channel layer is the dominant mechanism for the positive shift of the threshold voltage under negative gate bias in the enhancement mode GaN MOSFET. (c) 2015 The Japan Society of Applied Physics

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density D-it in MOS structures, Dit in the device with AlN was determined to be in the range of 10(11)-10(12) eV(-1) cm(-2), showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well. (C) 2015 AIP Publishing LLC.