This paper reports a normally-off high voltage hybrid Al203/GaN gate-recessed MOSFET fabricated on silicon substrate. The normally off operation was implemented by digital gate recess using an oxidation and wet etching based AlGaN barrier remove technique. The Al203/GaN MOSFET features a true normally off operation with a threshold voltage of 2 V extracted by the linear extrapolation of the transfer curve. The three terminal off-state breakdown voltage is 1650 V for the device with 30 gm gate-drain distance with floating Si substrate. The breakdown voltage is limited to 1000 V when the Si substrate is grounded. The on-resistance is 7.0 m Omega cm(2) for the device with 30 gm gate-drain distance and the power figure of merit is 388 MW/cm2. The small signal RF performance of the normally-off GaN MOSFET is also evaluated.

In this work, the performance of GaN-based MOS-Channel-HEMTs (MOSC-HEMTs) are shown to be greatly improved by a thin ALD-grown AlN interfacial layer inserted between the amorphous Al2O3 gate dielectric and GaN-channel. The single-crystalline AlN interfacial layer effectively blocks oxygen from the GaN surface and avoids the formation of detrimental Ga-O bonds. Frequency-dispersion in C-V characteristics has been effectively suppressed. The maximum drain current and field-effect mobility are boosted from 410 mA/mm and 98 cm(2)/V.s in a conventional Al2O3/GaN MOSC-HEMT to 660 mA/mm and 165 cm(2)/V.s in an Al2O3/AlN/GaN MOSC-HEMT, owing to improved interface quality. The devices also deliver a high ON/OFF current ratio of similar to 10(10), and significantly reduced dynamic on-resistance degradation.

High temperature characteristics of GaN-based inverter is presented from room temperature (RT) to 300 degrees C, which is integrated with enhancement-mode MOSFET and depletion-mode HEMT. At 300 degrees C, the fabricated inverter operates properly at a supply voltage (V-DD) of 7 V with 6.5 V for logic voltage swing, 3.3 V for threshold voltage (V-TH), 2.4 V for logic-low noise margin (NML), and 3.4 V for logic-high noise margin (NMH). Meanwhile, the inverter exhibits small variations from RT to 300 degrees C in terms of logic voltage swing, V-TH, NML, and NMH with the maximum relative variations of 2.2%, 5.7%, 12.9%, and 4.9% in such temperature range, respectively.

In this paper, we report the device performance of a high-voltage normally off Al2O3/GaN MOSFET on the Si substrate. Normally off operation is obtained by multiple cycles of O-2 plasma oxidation and wet oxide-removal gate recess process. The recessed normally off GaN MOSFET with 3 mu m gate-drain distance exhibits a maximum drain current of 585 mA/mm at 9 V gate bias. The threshold voltage of the MOSFET is 2.8 V with a standard derivation of 0.2 V on the sample with an area of 2 x 2 cm(2). The gate leakage current is below 10(-6) mA/mm during the whole gate swing up to 9 V and the I-ON/I-OFF ratio is larger than 10(9), indicating the good quality of Al2O3 gate insulator. The MOSFET with 10 mu m gate-drain distance shows a three terminal OFF-state breakdown voltage (BV) of 967 V at zero gate-source bias with a drain leakage current criterion of 1 mu A/mm. The specific ON-resistance (R-ON,R- SP) of the device is 1.6 m Omega . cm(2) and the power figure of merit (BV2/R-ON,R- SP) is 584 MW/cm(2).

A self-terminating gate recess wet etching technique with thermal oxidation of the AlGaN/GaN layer followed by etching in potassium hydroxide (KOH) solution was recently proposed by the present authors for normally-off AlGaN/GaN metal-oxide semiconductor field effect transistors (MOSFETs). In this present reported work, the oxidation process inside the AlGaN/GaN heterostructure involved in this technique was analysed using several material characterisation methods. The measurement results show that the concentration and depth of the O element distribution increase with increased thermal oxidation temperature. It is worth noting that after 650 degrees C oxidation almost no O element could be found in the GaN layer and the O element mainly locates in the AlGaN layer with an obvious correlation between the distribution of Al and O elements, where the Al(Ga)-oxide was detected by X-ray photoelectron spectroscopy, which could be etched by 70 degrees C KOH. Thus, self-terminating wet etching on the AlGaN/GaN material is achieved.

Based on our proposed self-terminating gate recess etching technique, normally-off recess-gated AlGaN/GaN MOSFET has been demonstrated with a novel method using GaN cap layer (CL) as recess mask, which, as a result, simplifies the device fabrication process and lowers the fabrication cost. The GaN CL is capable of acting as an effective recess mask for the gate recess process, which includes a thermal oxidation for 45 min at 650 degrees C followed by 4-min etching in potassium hydroxide (KOH) at 70 degrees C. After gate recess process, no obvious change is observed in terms of the surface morphology of the GaN CL, the contact resistance of the Ohmic contact formed directly on the GaN CL as well as the sheet resistance of the two-dimensional electron gas (2-DEG) channel layer under the GaN CL. The fabricated device exhibits a threshold voltage (V-th) as high as 5 V, a maximum drain current (I-dmax) of similar to 200 mA/mm, a high ON/OFF current ratio of similar to 10(10) together with a low forward gate leakage current of similar to 10(-5) mA/mm. Meanwhile, the OFF-state breakdown voltage (V-br) of the device with gate-drain distance of 6 mu m is 450 V.

Postgate annealing (PGA) in N-2/O-2 atmosphere at 300 degrees C for various annealing time is performed on enhancement mode AlGaN/GaN MOSFET fabricated using a self-terminating gate recess etching technique. After 45-min annealing, the device OFF-state leakage current decreases by more than two orders of magnitude and thus a low OFF-state leakage current of similar to 10(-13) A/mm is obtained at room temperature, resulting in an excellent ON/OFF current ratio of similar to 10(12). At 250 degrees C, the device still exhibits a low OFF-state leakage current of similar to 10(-9) A/mm and high ON/OFF current ratio of similar to 10(8). Meanwhile, a strong correlation between the OFF-state leakage current and mesa isolation current is observed as we change the annealing time: 1) the lower the mesa isolation current and 2) the lower the OFF-state leakage current and thus the higher the ON/OFF current ratio. It is the suppression of the mesa isolation current owing to the passivation of atomic layer deposition Al2O3 that leads to the improvement of the OFF-state leakage current and ON/OFF current ratio after PGA. Besides, the device shows no obvious change in terms of its threshold voltage and maximum drain current after PGA.

In this letter, we investigated the behaviors of surface-and buffer-induced current collapse in AlGaN/GaN high-electron mobility transistors (HEMTs) using a soft-switched pulsed I-V measurement with different quiescent bias points. It is found that the surface-and buffer-related current collapse have different relationship with the gate and drain biases (V-GS0, V-DS0) during quiescent bias stress. The surface-induced current collapse in devices without passivation monotonically increases with the negative V-GS0, suggesting that an electron injection to the surface from gate leakage is the dominant mechanism and the Si3N4 passivation could effectively eliminate such current collapse. The buffer-induced current collapse in devices with intentionally carbon-doped buffer layer exhibits a different relationship with V-GS0 after surface passivation. The buffer-related current collapse shows a bell-shaped behavior with V-GS0, suggesting that a hot electron trapping in the buffer is the dominant mechanism. The soft-switched pulsed I-V measurement provides an effective method to distinguish between the surface-and buffer-related current collapse in group III-nitride HEMTs.

A novel simple approach to extract parasitic source and drain resistances of high electron mobility transistors (HEMT) is presented. This method could obtain the parasitic resistances by determining the portion of channel resistance involved in the measured end-resistance based on the identification of the channel position corresponding to the measured floating-gate voltage with the floating-gate, drain-and source-current-injection configurations on a single device. The technique is demonstrated on AlGaN/GaN HEMTs. It is found that the ratio of the channel resistance involving in the end-resistance to the total channel resistance approaches to a constant independent on the gate length, which could simplify the practical application of this novel method. The experimental results show that the source and drain resistances extracted by this method coincide with series resistance extracted by traditional Transmission Line Model (TLM) measurement. (C) 2014 Elsevier Ltd. All rights reserved.

We report a high-performance normally-off Al2O3/AlN/GaN MOS-channel-high electron mobility transistor (MOSC-HEMT) featuring a monocrystalline AlN interfacial layer inserted between the amorphous Al2O3 gate dielectric and the GaN channel. The AlN interfacial layer effectively blocks oxygen from the GaN surface and prevents the formation of detrimental Ga-O bonds. Frequency-dispersion in C-V characteristics and threshold voltage hysteresis are effectively suppressed, owing to improved interface quality. The new MOSC-HEMTs exhibit a maximum drain current of 660 mA/mm, a field-effect mobility of 165 cm(2)/V . s, a high ON/OFF drain current ratio of similar to 10(10), and low dynamic ON-resistance degradation.