Jing Y, Sun Y, Wu M, Zhu Z, Zhou J, HUANG R, Ye L, Jia T. NeRF-Learner: A 2.79mJ/Frame NeRF-SLAM Processor with Unified Inference/Training Compute-in-Memory for Large-Scale Neural Rendering, in 50th European Solid-State Electronics Research Conference (ESSERC).; 2024.

Loscalzo E, Cochet M, Zuckerman J, Zaliasl S, Lekas M, Cahill S, Jia T, Swaminathan K, dos Santos MC, Giri D, et al. A 400-ns-Settling-Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12nm FinFET Technology, in IEEE Symposium on VLSI Technology & Circuits (VLSI).; 2024.

Dong Y, Liu X, Bai K, Li G, Wu M, Jing Y, Zhang Y, Zhan P, Zhang Y, Ma Y, et al. A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup, in IEEE Symposium on VLSI Technology & Circuits (VLSI).; 2024.

Cochet M, Swaminathan K, Loscalzo EJ, Zuckerman J, dos Santos MC, Giri D, Buyuktosunoglu A, Jia T, Brooks D, Wei G-Y, et al. BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs, in International Symposium on Computer Architecture (ISCA).; 2024.

Jing Y, Wu M, Zhou J, Sun Y, Ma Y, HUANG R, Ye L, Jia T. AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration, in Design Automation Conference (DAC).; 2024.

Chen Z, Ma Y, Li K, Jia Y, Li G, Wu M, Jia T, Ye L, HUANG R. An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology, in Design Automation Conference (DAC).; 2024.

Li M, Zhi Q, Dong Y, Ye L, Jia T. SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning, in Design Automation Conference (DAC).; 2024.

Qiu Y, Ma Y, Wu M, Jia Y, Qu X, Zhou Z, Lou J, Jia T, Ye L, HUANG R. Quartet: A 22nm 0.09mJ/inference digital compute-in-memory versatile AI accelerator with heterogeneous tensor engines and off-chip-less dataflow, in IEEE Custom Integrated Circuit Conference (CICC).; 2024.

Wu M, Ren W, Chen P, Zhao W, Jing Y, Ru J, Wang Z, Ma Y, HUANG R, Jia T, et al. S2D-CIM: A 22nm 128Kb systolic digital compute-in-memory macro with domino data path for flexible vector operation and 2-D weight update in edge AI applications, in IEEE Custom Integrated Circuit Conference (CICC).; 2024.

dos Santos* M C, Jia* T, J. Zuckerman*, M. Cochet*, D. Giri, Loscalzo E, K. Swaminathan, T. Tambe, Zhang J, A. Buyuktosunoglu, et al. A 12nm Linux-SMP-capable RISC-V SoC with 14 accelerator types, distributed hardware power management and flexible NoC-based data orchestration, in IEEE International Solid-State Circuits Conference (ISSCC).; 2024.

Y. Liu, Y. Ma, N. Shang, T. Zhao, P. Chen, M. Wu, J. Ru, T. Jia, L. Ye, Z. Wang, et al. A 22nm 0.26nW/synapse spike-driven spiking neural network processing unit using time-step-first dataflow and sparsity-adaptive in-memory computing, in IEEE International Solid-State Circuits Conference (ISSCC).; 2024.

Chen P, Wu M, Zhao W, Ma Y, Jia T, Ye L. A 44.3 TOPS/W SRAM Compute-in-Memory with Near-CIM Analog Memory and Activation for DAC/ADC-less Operations. IEEE Solid-State Circuits Letters. 2024.

Ma Y, Qiu Y, Zhao W, Wu M, Jia T, Ye L, HUANG R. DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. IEEE Transactions on Circuits and Systems I: Regular Papers. 2024.

Liu Y, Chen Z, Zhao W, Zhao T, Jia T, Wang Z, HUANG R, Ye L, Ma Y. Sparsity-Aware In-Memory Neuromorphic Computing Unit with Configurable Topology of Hybrid Spiking and Artificial Neural Network. IEEE Transactions on Circuits and Systems I: Regular Papers. 2024.

Hsiao Y-S, Wan Z, Jia T, Ghosal R, Mahmoud A, Raychowdhury A, Brooks D, Wei G-Y, Reddi VJ. Silent data corruption in robot operating system: A case for end-to-end system-level fault analysis using autonomous UAVs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2024.

Tombesi G, Zuckerman J, Mantovani P, Giri D, dos Santos MC, Jia T, Brooks D, Wei G-Y, Carloni LP. SoCProbe: Compositional post-silicon validation of heterogeneous NoC-based SoCs (Best-Paper Award), in International Symposium on Networks‑on‑Chip (NOCS).; 2023.

Dong Y, Jia T, Du K, Jing Y, Wang Q, Zhan P, Zhang Y, Yan F, Ma Y, Liang Y, et al. A model-specific end-to-end design methodology for resource-constrained TinyML hardware, in Design Automation Conference (DAC).; 2023.

Chen X, Shoukry A, Jia T, Zhang X, Magod R, Desai N, Gu J. A 65nm fully-integrated fast-switching buck converter with resonant gate drive and automatic tracking, in IEEE Custom Integrated Circuit Conference (CICC).; 2023.

Cui X, Zheng S, Jia T, Ye L, Liang Y. ARES: A mapping framework of DNNs towards diverse PIMs with general abstractions, in International Conference on Computer Aided Design (ICCAD). Nov ; 2023.

Jing Y, Sun Y, Wang X, Zhao W, Wu M, Yan F, Ma Y, Ye L, Jia T. CIM-3DRec: A 3D reconstruction accelerator with digital computing-in-memory and Octree-based scheduler, in IEEE International Symposium on Low Power Electronics and Design (ISLPED).; 2023.