Tombesi G, Zuckerman J, Mantovani P, Giri D, dos Santos MC, Jia T, Brooks D, Wei G-Y, Carloni LP. SoCProbe: Compositional post-silicon validation of heterogeneous NoC-based SoCs (Best-Paper Award), in International Symposium on Networks‑on‑Chip (NOCS).; 2023.

Dong Y, Jia T, Du K, Jing Y, Wang Q, Zhan P, Zhang Y, Yan F, Ma Y, Liang Y, et al. A model-specific end-to-end design methodology for resource-constrained TinyML hardware, in Design Automation Conference (DAC).; 2023.

Chen X, Shoukry A, Jia T, Zhang X, Magod R, Desai N, Gu J. A 65nm fully-integrated fast-switching buck converter with resonant gate drive and automatic tracking, in IEEE Custom Integrated Circuit Conference (CICC).; 2023.

Cui X, Zheng S, Jia T, Ye L, Liang Y. ARES: A mapping framework of DNNs towards diverse PIMs with general abstractions, in International Conference on Computer Aided Design (ICCAD). Nov ; 2023.

Jing Y, Sun Y, Wang X, Zhao W, Wu M, Yan F, Ma Y, Ye L, Jia T. CIM-3DRec: A 3D reconstruction accelerator with digital computing-in-memory and Octree-based scheduler, in IEEE International Symposium on Low Power Electronics and Design (ISLPED).; 2023.

Liu Y, Chen Z, Wang Z, Zhao W, He W, Zhu J, Wang Q, Zhang N, Jia T, Ma Y, et al. A 22nm 0.43pJ/SOP sparsity-aware in-memory neuromorphic computing system with hybrid spiking and artificial neural network and configurable topology, in IEEE Custom Integrated Circuits Conference (CICC).; 2023.

Tambe T, Zhang J, Hooper C, Jia T, Whatmough PN, Zuckerman J, Santos CDM, Loscalzo EJ, Giri D, Shepard K, et al. A 12nm 18.1TFLOPs/W sparse transformer processor with entropy-based early exit, mixed-precision predication and fine-grained power management, in IEEE International Solid-State Circuits Conference (ISSCC).; 2023.

Chen P, Wu M, Zhao W, Cui J, Wang Z, Zhang Y, Wang Q, Ru J, Shen L, Jia T, et al. A 22-nm delta-sigma computing-in-memory (ΔΣCIM) SRAM macro with near-zero-mean outputs and LSB-first ADCs achieving 21.38TOPS/W for 8b-MAC edge AI processing, in IEEE International Solid-State Circuits Conference (ISSCC).; 2023.

Zacharopoulos G, Ejjeh A, Jing Y, Yang E-Y, Jia T, Brumar I, Intan J, Huzaifa M, Adve S, Adve V, et al. Trireme: Exploration of hierarchical multi-Level parallelism for hardware acceleration. ACM Transactions on Embedded Computing Systems. 2023.

Hsiao Y-S, Wan Z, Jia T, Ghosal R, Mahmoud A, Raychowdhury A, Brooks D, Wei G-Y, Reddi VJ. MAVFI: An end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles, in Design, Automation and Test in Europe (DATE).; 2023.

Jia T, Mantovani P, dos Santos MC, Giri D, Zuckerman J, Loscalzo EJ, Cochet M, Swaminathan K, Tombesi G, Zhang JJ, et al. A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC, in European Solid-State Circuits Conference (ESSCIRC).; 2022.

Ju Y, Guo S, Liu Z, Jia T, Gu J. A differentiable neural computer for logic reasoning with scalable near-memory computing and sparsity based enhancement, in European Solid-State Circuits Conference (ESSCIRC).; 2022.

dos Santos MC, Jia T, Cochet M, Swaminathan K, Zuckerman J, Mantovani P, Giri D, Zhang JJ, Loscalzo EJ, Tombesi G, et al. (invited paper) A scalable methodology for agile chip development with open-source hardware components, in International Conference on Computer-Aided Design (ICCAD).; 2022.

Jia T, Yang E-Y, Hsiao Y-S, Cruz J, Brooks D, Wei G-Y, Reddi VJ. OMU: A probabilistic 3D occupancy mapping accelerator for real-time OctoMap at the edge, in Design, Automation and Test in Europe (DATE).; 2022.

Wan Z, Anwar A, Mahmoud A, Jia T, Hsiao Y-S, Reddi VJ, Raychowdhury A. FRL-FI: Fault tolerance analysis and improvement of federated reinforcement learning-based navigation systems, in Design, Automation and Test in Europe (DATE).; 2022.

Tambe T, Hooper C, Pentecost L, Jia T, Yang E-Y, Donato M, Sanh V, Whatmough P, Rush A, Brooks D, et al. EdgeBERT: sentence-level energy optimizations for latency-aware multi-task NLP inference, in International Symposium on Microarchitecture (MICRO).; 2021.

Wan Z, Anwar A, Hsiao Y-S, Jia T, Reddi VJ, Raychowdhury A. Analyzing and improving fault tolerance of learning-based navigation system, in Design Automation Conference (DAC).; 2021.

Yang E-Y, Jia T, Brooks D, Wei G-Y. FlexACC: A programmable accelerator with application-specific ISA for flexible deep neural network inference, in International Conference on Application-specific Systems, Architectures and Processors (ASAP).; 2021.

Jia T, Ju Y, Joseph R, Gu J. NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance, in International Symposium on Microarchitecture (MICRO).; 2020.

Jia T, Ju Y, Gu J. A compute-adaptive elastic clock chain technique with dynamic timing enhancement for 2D PE array based accelerators, in International Solid-State Circuits Conference (ISSCC).; 2020.