Takken T, Ferencz A, Wu C-S, McAuliffe L, Jia T, Zhang X. A 48V input 0.75V output DC-DC converter power block for HPC systems and datacenters(invited), in VLSI Symposium on Circuits (VLSI).; 2019.

Jia T, Joseph R, Gu J. An instruction-driven adaptive clock management through dynamic phase scaling and compiler assistance for a low power microprocessor. IEEE Journal of Solid-State Circuits (JSSC). 2019.

Jia T, Joseph R, Gu J. An adaptive clock management scheme exploiting instruction-based dynamic timing slack for general-purpose graphic processor unit with deep pipeline and out-of-order execution, in International Solid-State Circuits Conference (ISSCC).; 2019.