Agile-Designed Domain-Specific SoC Design and Methodology

We develop a domain-specific SoC for next generation smart, connected autonomous vehicles. The SoC is designed with highly heterogeneous CPU, AI accelerators, and other specialized accelerators. The SoC design adopts agile HLS design methodology, and based on the open-source Embedded Scalable Platform (ESP).

Compute-in-Memory for Efficient AI Processing

Compute-in-memory (CIM) technique has been proven as an efficient computing paradigm to alleviate the memory wall bottleneck. We develop efficient accelerator architecture and chips using digital SRAM-based CIM macros. The target AI applications include Transformer, 3D vision processing, etc.

Efficiect Heterogeneous TinyML Architecture at Edge

Energy efficiency is the key development target for power-constrained edge devices. We develop architecture exploration framework and TinyML chips for end-to-end edge applications, e.g. audio, vision. We also consider the on-device learning and power management techniques for edge AI chip design.