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* Corresponding Author

2025

  1. [ISSCC] Yiqi Jing, Jiaqi Zhou, Yiyang Sun, Siyuan He, Ru Huang, Le Ye*, Tianyu Jia*, 37.6 A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2025.

  2. [DATE] Zhantong Zhu, Hongou Li, Wenjie Ren, Meng Wu, Le Ye, Ru Huang, Tianyu Jia*, Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs, Design, Automation and Test in Europe Conference (DATE), Mar. 2025.

  3. [ASP-DAC] Yiyang Sun, Peiran Yan, Yiqi Jing, Le Ye, Tianyu Jia*, GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization, 30th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2025.

2024

  1. [ICCAD] Yanchi Dong, Xueping Liu, Xiaochen Hao, Yun (Eric) Liang, Ru Huang, Le Ye, Tianyu Jia*, Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Oct. 2024.

  2. [ICCAD] Qipan Wang, Xueqing Li, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang, ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Oct. 2024.

  3. [ESSERC] Yiqi Jing, Yiyang Sun, Meng Wu, Zhaolongtai Zhu, Jiaqi Zhou, Ru Huang, Le Ye, Tianyu Jia*, NeRF-Learner: A 2.79mJ/Frame NeRF-SLAM Processor with Unified Inference/Training Compute-in-Memory for Large-Scale Neural Rendering, 50th European Solid-State Electronics Research Conference (ESSERC), Sep. 2024.

  4. [VLSI] Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye*, Tianyu Jia*, A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup, IEEE Symposium on VLSI Technology & Circuits (VLSI), Jun. 2024.

  5. [VLSI] Erik Loscalzo, Martin Cochet, Joseph Zuckerman, Samira Zaliasl, Michael Lekas, Stephen Cahill, Tianyu Jia, Karthik Swaminathan, Maico Cassel dos Santos, Davide Giri, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, David Brooks, Gu-Yeon Wei, Luca Carloni, Pradip Bose, Kenneth Shepard, A 400-ns-Settling-Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFETTechnology, IEEE Symposium on VLSI Technology & Circuits (VLSI), Jun. 2024.

  6. [DAC] Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Le Ye*, Tianyu Jia*, AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration, IEEE Design Automation Conference (DAC), Jun. 2024.

  7. [DAC] Mingxuan Li, Qinzhe Zhi, Yanchi Dong, Le Ye, Tianyu Jia*, SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning, IEEE Design Automation Conference (DAC), Jun. 2024.

  8. [DAC] Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang, An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology, IEEE Design Automation Conference (DAC), Jun. 2024.

  9. [ISCA] Martin Cochet, Karthik Swaminathan, Erik Jens Loscalzo, Joseph Zuckerman, Maico Cassel dos Santos, Davide Giri, Alper Buyuktosunoglu, Tianyu Jia, David Brooks, Gu-Yeon Wei, Kenneth Shepard, Luca P. Carloni, and Pradip Bose, BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs, International Symposium on Computer Architecture (ISCA), Jul. 2024.

  10. [CICC] Meng Wu, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, Yufei Ma, Ru Huang, Tianyu Jia*, Le Ye*, S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications, IEEE Custom Integrated Circuit Conference (CICC), Apr. 2024.

  11. [CICC] Yikan Qiu, Yufei Ma, Meng Wu, Yifan Jia, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, Ru Huang, Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow, IEEE Custom Integrated Circuit Conference (CICC), Apr. 2024.

  12. [ISSCC] Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, Tianyu Jia, Le Ye, Zhixuan Wang, Ru Huang, 30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. 

  13. [ISSCC] Maico Cassel dos Santos†, Tianyu Jia†, Joseph Zuckerman†, Martin Cochet†, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei, 14.5 A 12nm Linux-SMP-capable RISC-V SoC with 14 accelerator types, distributed hardware power management and flexible NoC-based data orchestration, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. († Equal Contributions)

  14. [SSC-L] Peiyu Chen, Meng Wu, Wentan Zhao, Yufei Ma, Tianyu Jia*, Le Ye, A 44.3 TOPS/W SRAM Compute-in-Memory with Near-CIM Analog Memory and Activation for DAC/ADC-less Operations, IEEE Solid-State Circuits Letters (SSC-L), 2024.

  15. [SSC-L] Meng Wu, Wenjie Ren, Peiyu Chen, Wentan Zhao, Tianyu Jia*, Le Ye*, S2D-CIM: SRAM-based Systolic Digital Compute-in-Memory Framework with Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update, IEEE Solid-State Circuits Letters (SSC-L), 2024. (CICC invited)

  16. [TCAS-I] Yufei Ma, Yikan Qiu, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang, DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network, IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.

  17. [TCAS-I] Ying Liu, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang, Ru Huang, Le Ye, Yufei Ma, Sparsity-Aware In-Memory Neuromorphic Computing Unit with Configurable Topology of Hybrid Spiking and Artificial Neural Network, IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.

  18. [TCAD] Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Reddi, Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs,  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.

2023

  1. [ICCAD] Xiuping Cui, Size Zheng, Tianyu Jia, Le Ye, Yun Liang, ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions, IEEE International Conference on Computer Aided Design (ICCAD), Nov. 2023.

  2. [ISLPED] Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, Tianyu Jia*, DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler, IEEE  International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2023.

  3. [DAC] Yanchi Dong, Tianyu Jia*, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang, A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware, IEEE Design Automation Conference (DAC), Jun. 2023.

  4. [CICC] Ying Liu, Zhiyuan Chen, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Qijun Wang, Ning Zhang, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang, A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology, IEEE Custom Integrated Circuit Conference (CICC), Apr. 2023.

  5. [CICC] Xi Chen, Aly Shoukry, Tianyu Jia, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu, A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking, IEEE Custom Integrated Circuit Conference (CICC), Apr. 2023.

  6. [DATE] Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi, MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles, Design, Automation and Test in Europe Conference (DATE), Apr. 2023.

  7. [ISSCC] Peiyu Chen, Meng Wu, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang, 7.8 A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.

  8. [ISSCC] Thierry Tambe, Jeff Zhang, Coleman Hooper, Tianyu Jia, Paul N. Whatmough, Joseph Zuckerman, Maico Cassel Dos Santos, Erik Jens Loscalzo, Davide Giri, Kenneth Shepard, Luca Carloni, Alexander Rush, David Brooks, Gu-Yeon Wei, 22.9 A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.

  9. [IEEE Design & Test] Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P. Carloni, SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs, IEEE Design & Test, 2023. (NOCS Best Paper Award)

  10. [ACM] Georgios Zacharopoulos, Adel Ejjeh, Ying Jing, En-Yu Yang, Tianyu Jia, Iulian Brumar, Jeremy Intan, Muhammad Huzaifa, Sarita Adve, Vikram Adve, Gu-Yeon Wei, David Brooks, Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration, ACM Transactions on Embedded Computing Systems, 2023.

2022

  1. [ICCAD] Maico Cassel dos Santos†, Tianyu Jia†, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth Shepard, Luca P. Carloni, Pradip Bose, A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components, IEEE International Conference on Computer Aided Design (ICCAD), Nov. 2022. († Equal Contributions, Invited Paper)

  2. [ESSCIRC] Tianyu Jia†, Paolo Mantovani†, Maico Cassel dos Santos†, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy,  John-David Wellman, Kevin Tien, Luca Carloni, Kenneth Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose, A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC, European Solid-State Circuits Conference (ESSCIRC), Sep. 2022. († Equal Contributions)

  3. [ESSCIRC] Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu, A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement, European Solid-State Circuits Conference (ESSCIRC), Sep. 2022.

  4. [DATE] Tianyu Jia, En-Yu Yang, Yu-Shun Hsiao, Jonathan Cruz, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi, OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge, Design, Automation and Test in Europe Conference (DATE), Apr. 2022.

  5. [DATE] Zishen Wan, Aqeel Anwar, Abdulrahman Mahmoud, Tianyu Jia, Yu-Shun Hsiao, Vijay Janapa Reddi, Arijit Raychowdhury, FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems, Design, Automation and Test in Europe Conference (DATE), Apr. 2022.

2021

  1. [MICRO] Thierry Tambe, Coleman Hooper, Lillian Pentecost, Tianyu Jia, En-Yu Yang, Marco Donato, Victor Sanh, Paul N. Whatmough, Alexander M. Rush, David Brooks, Gu-Yeon Wei, EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference, IEEE International Symposium on Microarchitecture (MICRO), Nov. 2021. 

  2. [DAC] Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury, Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems, IEEE Design Automation Conference (DAC), Jun. 2021.

  3. [ASAP] En-Yu Yang, Tianyu Jia, David Brooks, Gu-Yeon Wei, FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference, IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP), Jul. 2021.

  4. [JSSC] Tianyu Jia, Yuhao Ju, Jie Gu, A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique, IEEE Journal of Solid-State Circuits, 2021.

2020

  1. [MICRO] Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu, NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance, IEEE International Symposium on Microarchitecture (MICRO), Nov. 2020. 

  2. [JSSC] Tianyu Jia, Yijie Wei, Russ Joseph, Jie Gu, An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture, IEEE Journal of Solid-State Circuits, 2020.

  3. [ISSCC] Tianyu Jia, Yuhao Ju, Jie Gu, 31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.

  4. [ECCE] Dongkwun Kim, Yoshitaka Yamauchi, Xiaodong Meng, Tianyu Jia, Liam McAuliffe, Todd Takken, Kevin Tien, Shuron Tian, Yuan Yao, Andrew Ferencz, Mingoo Seok, Xin Zhang, An Integrated Programmable Gate Timing Control and Gate Driver Chip for A 48V-to-0.75V Active-Clamp Forward Converter Power Block, IEEE Energy Conversion Congress and Exposition (ECCE), 2020.

2019 and before

  1. [JSSC] Tianyu Jia, Russ Joseph, Jie Gu, An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor, IEEE Journal of Solid-State Circuits, 2019. 

  2. [VLSI] Todd Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang, A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters, IEEE 2019 Symposium on VLSI Circuits, Jun. 2019.

  3. [ISSCC] Tianyu Jia, Russ Joseph, Jie Gu, 19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019.

  4. [ICCAD] Kofi Otseidu, Tianyu Jia, Joshua Bryne, Levi Hargrove, Jie Gu, Design and Optimization of Edge Computing Distributed Neural Processor for Biomedical Rehabilitation with Sensor Fusion, IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2018.

  5. [A-SSCC] Tianyu Jia, Jie Gu, A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications, IEEE International Conference on Computer Aided Design (ICCAD), Nov. 2018.

  6. [ESSCIRC] Tianyu Jia, Russ Joseph, Jie Gu, An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor, European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.

  7. [SOCC] Josiah Hester, Tianyu Jia, Jie Gu, Holistic Energy Management with uProcessor Co-Optimization in Fully Integrated Battery-Less IoTs, IEEE International System-on-Chip Conference (SOCC), Sep. 2018.

  8. [DAC] Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph, Compiler-guided instruction-level clock scheduling for timing speculative processors, IEEE Design Automation Conference (DAC), Jun. 2018.

  9. [JSSC] Tianyu Jia, Jie Gu, A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications, IEEE Journal of Solid-State Circuits, 2018.

  10. [VLSI] Tianyu Jia, Jie Gu, A 0.3-0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications, IEEE 2017 Symposium on VLSI Circuits, Jun. 2017.

  11. [DAC] Tianyu Jia, Russ Joseph, Jie Gu, Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management, IEEE Design Automation Conference (DAC), Jun. 2017.

  12. [MWSCAS] Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu, Software-guided greybox design methodology with integrated power and clock management, IEEE Design Automation Conference (DAC), Jun. 2017. (Invited Paper)

  13. [DAC] Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu, Exploration of associative power management with instruction governed operation for ultra-low power design, IEEE Design Automation Conference (DAC), Jun. 2016.

  14. [ESSCIRC] Yue Wu, Tianyu Jia, Bo Xia, Xinlong Ma, Li Kang, Xiaodong Yang, Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits, European Solid-State Circuits Conference (ESSCIRC), Sep. 2015.