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贾天宇 Tianyu Jia
北京大学集成电路学院
助理教授,研究员 / Assistant Professor
tianyuj@pku.edu.cn
联系方式
北京市海淀区颐和园路5号
北京大学微纳电子大厦
100871
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科研成果 by Year: 2017
2017
Jia T, Joseph R, Gu J
.
Greybox design methodology: a program driven hardware co-optimization with ultra-dynamic clock management
, in
Design Automation Conference (DAC)
.; 2017.
Jia T, Gu J
.
A 0.3-0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications
, in
VLSI Symposium on Circuits (VLSI)
.; 2017.
Jia T, Fan Y, Joseph R, Gu J
.
Software-guided greybox design methodology with integrated power and clock management
(invited)
, in
International Midwest Symposium on Circuits and Systems (MWSCAS)
.; 2017.
Recent Publications
NeRF-Learner: A 2.79mJ/Frame NeRF-SLAM Processor with Unified Inference/Training Compute-in-Memory for Large-Scale Neural Rendering
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup
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Overview
2024
(15)
2023
(10)
2022
(5)
2021
(3)
2020
(5)
2019
(3)
2018
(6)
2017
(3)
2016
(1)
2015
(1)