科研成果 by Year: 2020

2020
Jia T, Ju Y, Joseph R, Gu J. NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance, in International Symposium on Microarchitecture (MICRO).; 2020.
Jia T, Ju Y, Gu J. A compute-adaptive elastic clock chain technique with dynamic timing enhancement for 2D PE array based accelerators, in International Solid-State Circuits Conference (ISSCC).; 2020.
Jia T, Ju Y, Gu J. A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique. IEEE Journal of Solid-State Circuits (JSSC). 2020.
Jia T, Wei Y, Joseph R, Gu J. An adaptive clock scheme exploiting instruction-based dynamic timing slack for a GPGPU architecture. IEEE Journal of Solid-State Circuits (JSSC). 2020.
Kim D, Yamauchi Y, Meng X, Jia T, McAuliffe L, Takken T, Tien K, Tian S, Yao Y, Ferencz A, et al. An integrated programmable gate timing control and gate driver chip for a 48V-to-0.75V active-clamp forward converter power block, in Energy Conversion Congress and Exposition (ECCE).; 2020.