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贾天宇 Tianyu Jia
北京大学集成电路学院
助理教授,研究员 / Assistant Professor
tianyuj@pku.edu.cn
联系方式
北京市海淀区颐和园路5号
北京大学微纳电子大厦
100871
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科研成果 by Year: 2020
2020
Jia T, Ju Y, Joseph R, Gu J
.
NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance
, in
International Symposium on Microarchitecture (MICRO)
.; 2020.
Jia T, Ju Y, Gu J
.
A compute-adaptive elastic clock chain technique with dynamic timing enhancement for 2D PE array based accelerators
, in
International Solid-State Circuits Conference (ISSCC)
.; 2020.
Jia T, Ju Y, Gu J
.
A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique
. IEEE Journal of Solid-State Circuits (JSSC). 2020.
Jia T, Wei Y, Joseph R, Gu J
.
An adaptive clock scheme exploiting instruction-based dynamic timing slack for a GPGPU architecture
. IEEE Journal of Solid-State Circuits (JSSC). 2020.
Kim D, Yamauchi Y, Meng X, Jia T, McAuliffe L, Takken T, Tien K, Tian S, Yao Y, Ferencz A, et al.
An integrated programmable gate timing control and gate driver chip for a 48V-to-0.75V active-clamp forward converter power block
, in
Energy Conversion Congress and Exposition (ECCE)
.; 2020.
Recent Publications
NeRF-Learner: A 2.79mJ/Frame NeRF-SLAM Processor with Unified Inference/Training Compute-in-Memory for Large-Scale Neural Rendering
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup
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Overview
2024
(15)
2023
(10)
2022
(5)
2021
(3)
2020
(5)
2019
(3)
2018
(6)
2017
(3)
2016
(1)
2015
(1)