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贾天宇 Tianyu Jia
北京大学集成电路学院
助理教授,研究员 / Assistant Professor
tianyuj@pku.edu.cn
联系方式
北京市海淀区颐和园路5号
北京大学微纳电子大厦
100871
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科研成果
2019
Jia T, Joseph R, Gu J
.
An instruction-driven adaptive clock management through dynamic phase scaling and compiler assistance for a low power microprocessor
. IEEE Journal of Solid-State Circuits (JSSC). 2019.
2018
Jia T, Joseph R, Gu J
.
An instruction driven adaptive clock phase scaling with timing encoding and online instruction calibration for a low power microprocessor
, in
European Solid-State Circuits Conference (ESSCIRC)
.; 2018.
Jia T, Gu J
.
A fully-integrated LC-oscillator based buck regulator with autonomous resonant switching for low-power applications
, in
Asian Solid-State Circuits Conference (A-SSCC)
.; 2018.
Otseidu K, Jia T, Bryne J, Hargrove L, Gu J
.
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion
, in
International Conference on Computer-Aided Design (ICCAD)
.; 2018.
Hester J, Jia T, Gu J
.
Holistic energy management with uProcessor co-optimization in fully integrated battery-less IoTs
, in
International System-on-Chip Conference (SOCC)
.; 2018.
Fan Y, Jia T, Gu J, Campanoni S, Joseph R
.
Compiler-guided fine-grained clock adjustment for timing speculative processor
. Design Automation Conference (DAC). 2018.
Jia T, Gu J
.
A fully integrated buck regulator with 2-GHz resonant switching for low-power applications
. IEEE Journal of Solid-State Circuits (JSSC). 2018.
2017
Jia T, Gu J
.
A 0.3-0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications
, in
VLSI Symposium on Circuits (VLSI)
.; 2017.
Jia T, Joseph R, Gu J
.
Greybox design methodology: a program driven hardware co-optimization with ultra-dynamic clock management
, in
Design Automation Conference (DAC)
.; 2017.
Jia T, Fan Y, Joseph R, Gu J
.
Software-guided greybox design methodology with integrated power and clock management
(invited)
, in
International Midwest Symposium on Circuits and Systems (MWSCAS)
.; 2017.
2016
Jia T, Fan Y, Joseph R, Gu J
.
Exploration of associative power management with instruction governed operation for ultra-low power design
, in
Design Automation Conference (DAC)
.; 2016.
2015
Wu Y, Jia T, Xia B, Ma X, Kang L, Yang X
.
Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits
, in
European Solid-State Circuits Conference (ESSCIRC)
.; 2015.
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Recent Publications
NeRF-Learner: A 2.79mJ/Frame NeRF-SLAM Processor with Unified Inference/Training Compute-in-Memory for Large-Scale Neural Rendering
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup
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