Liu Y, Chen Z, Wang Z, Zhao W, He W, Zhu J, Wang Q, Zhang N, Jia T, Ma Y, et al. A 22nm 0.43pJ/SOP sparsity-aware in-memory neuromorphic computing system with hybrid spiking and artificial neural network and configurable topology, in IEEE Custom Integrated Circuits Conference (CICC).; 2023.

Tambe T, Zhang J, Hooper C, Jia T, Whatmough PN, Zuckerman J, Santos CDM, Loscalzo EJ, Giri D, Shepard K, et al. A 12nm 18.1TFLOPs/W sparse transformer processor with entropy-based early exit, mixed-precision predication and fine-grained power management, in IEEE International Solid-State Circuits Conference (ISSCC).; 2023.

Chen P, Wu M, Zhao W, Cui J, Wang Z, Zhang Y, Wang Q, Ru J, Shen L, Jia T, et al. A 22-nm delta-sigma computing-in-memory (ΔΣCIM) SRAM macro with near-zero-mean outputs and LSB-first ADCs achieving 21.38TOPS/W for 8b-MAC edge AI processing, in IEEE International Solid-State Circuits Conference (ISSCC).; 2023.

Zacharopoulos G, Ejjeh A, Jing Y, Yang E-Y, Jia T, Brumar I, Intan J, Huzaifa M, Adve S, Adve V, et al. Trireme: Exploration of hierarchical multi-Level parallelism for hardware acceleration. ACM Transactions on Embedded Computing Systems. 2023.

Hsiao Y-S, Wan Z, Jia T, Ghosal R, Mahmoud A, Raychowdhury A, Brooks D, Wei G-Y, Reddi VJ. MAVFI: An end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles, in Design, Automation and Test in Europe (DATE).; 2023.

Jia T, Mantovani P, dos Santos MC, Giri D, Zuckerman J, Loscalzo EJ, Cochet M, Swaminathan K, Tombesi G, Zhang JJ, et al. A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC, in European Solid-State Circuits Conference (ESSCIRC).; 2022.

Ju Y, Guo S, Liu Z, Jia T, Gu J. A differentiable neural computer for logic reasoning with scalable near-memory computing and sparsity based enhancement, in European Solid-State Circuits Conference (ESSCIRC).; 2022.

dos Santos MC, Jia T, Cochet M, Swaminathan K, Zuckerman J, Mantovani P, Giri D, Zhang JJ, Loscalzo EJ, Tombesi G, et al. (invited paper) A scalable methodology for agile chip development with open-source hardware components, in International Conference on Computer-Aided Design (ICCAD).; 2022.

Jia T, Yang E-Y, Hsiao Y-S, Cruz J, Brooks D, Wei G-Y, Reddi VJ. OMU: A probabilistic 3D occupancy mapping accelerator for real-time OctoMap at the edge, in Design, Automation and Test in Europe (DATE).; 2022.

Wan Z, Anwar A, Mahmoud A, Jia T, Hsiao Y-S, Reddi VJ, Raychowdhury A. FRL-FI: Fault tolerance analysis and improvement of federated reinforcement learning-based navigation systems, in Design, Automation and Test in Europe (DATE).; 2022.

Tambe T, Hooper C, Pentecost L, Jia T, Yang E-Y, Donato M, Sanh V, Whatmough P, Rush A, Brooks D, et al. EdgeBERT: sentence-level energy optimizations for latency-aware multi-task NLP inference, in International Symposium on Microarchitecture (MICRO).; 2021.

Wan Z, Anwar A, Hsiao Y-S, Jia T, Reddi VJ, Raychowdhury A. Analyzing and improving fault tolerance of learning-based navigation system, in Design Automation Conference (DAC).; 2021.

Yang E-Y, Jia T, Brooks D, Wei G-Y. FlexACC: A programmable accelerator with application-specific ISA for flexible deep neural network inference, in International Conference on Application-specific Systems, Architectures and Processors (ASAP).; 2021.

Jia T, Ju Y, Joseph R, Gu J. NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance, in International Symposium on Microarchitecture (MICRO).; 2020.

Jia T, Ju Y, Gu J. A compute-adaptive elastic clock chain technique with dynamic timing enhancement for 2D PE array based accelerators, in International Solid-State Circuits Conference (ISSCC).; 2020.

Kim D, Yamauchi Y, Meng X, Jia T, McAuliffe L, Takken T, Tien K, Tian S, Yao Y, Ferencz A, et al. An integrated programmable gate timing control and gate driver chip for a 48V-to-0.75V active-clamp forward converter power block, in Energy Conversion Congress and Exposition (ECCE).; 2020.

Jia T, Wei Y, Joseph R, Gu J. An adaptive clock scheme exploiting instruction-based dynamic timing slack for a GPGPU architecture. IEEE Journal of Solid-State Circuits (JSSC). 2020.

Jia T, Ju Y, Gu J. A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique. IEEE Journal of Solid-State Circuits (JSSC). 2020.

Jia T, Joseph R, Gu J. An adaptive clock management scheme exploiting instruction-based dynamic timing slack for general-purpose graphic processor unit with deep pipeline and out-of-order execution, in International Solid-State Circuits Conference (ISSCC).; 2019.

Takken T, Ferencz A, Wu C-S, McAuliffe L, Jia T, Zhang X. A 48V input 0.75V output DC-DC converter power block for HPC systems and datacenters(invited), in VLSI Symposium on Circuits (VLSI).; 2019.