High-precision large dynamic-range (DR) current-sensing front-ends are widely used in biomedical applications, such as patch-clamp, molecular concentration detection, and gene sequencing. The new gene sequencers require low-noise analog front-ends capable of sensing large DR current (>100 dB) down to sub-pA-level. At this level of precision, oversampled data converters are usually used. However, given the limited oversampling ratio in high throughput applications, it is very challenging to achieve a sub-pA-level sensitivity and >100dB DR within the limited area and energy budgets [1]. In [2], a 140dB DR is achieved using a multi-bit delta-sigma modulator (DSM), but the power consumption is over 1mW and the current sensitivity is limited to 6.3pA. An hourglass ADC achieving a 100fA sensitivity and 140dB DR is presented in [3], but is limited by conversion rate and relatively high power consumption (295μW). For a 100Hz bandwidth, its noise floor increases to 18pA.

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance tradeoffs, and fast technology advancements. Although there have been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.

In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS layout automation tools comes to a large extent from the difficulty in comprehending and incorporating designer expertise. To mimic the behavior of experienced designers in well generation, we propose a generative adversarial network (GAN) guided well generation framework with a post-refinement stage leveraging the previous high-quality manually-crafted layouts. Guiding regions for wells are first created by a trained GAN model, after which the well generation results are legalized through post-refinement to satisfy design rules. Experimental results show that the proposed technique is able to generate wells close to manual designs with comparable post-layout circuit performance.

This paper presents a highly power efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves 6-time current reuse, thereby significantly boosting gm and lowering noise but without increasing power. A novel biasing scheme is devised to ensure robust operation under 1V supply. A prototype in 180nm CMOS has 5.5uV rms noise within 10kHz BW while consuming only 0.25uW, leading to a noise efficiency factor (NEF) of 1.07, which is the best among reported amplifiers.