Date Presented:

June

摘要:

This paper presents a highly power efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves 6-time current reuse, thereby significantly boosting gm and lowering noise but without increasing power. A novel biasing scheme is devised to ensure robust operation under 1V supply. A prototype in 180nm CMOS has 5.5uV rms noise within 10kHz BW while consuming only 0.25uW, leading to a noise efficiency factor (NEF) of 1.07, which is the best among reported amplifiers.