Our CICC 2024 paper of "An 8b 1GS/s SAR ADC with Metastability-based Resolution/Speed Enhancement and Self-tuning delay Achieving 47.2dB SNDR at Nyquist Input" has been selected as the 2024 IEEE Custom Integrated Circuit Conference (CICC) Outstanding Student Paper Award. Congrats to Jie Li, Siyuan Ye, and the rest of the whole team! 

The prototype chip was designed, measured by Jie Li. We thanks Prof. Huang, and PKU School of Integrated Circuit for all the resources and support.  阅读更多有关 课题组荣获CICC杰出学生论文奖！恭喜李杰

The paper from our group has been accepted to ISSCC 2024, whose title is "A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique". 阅读更多有关 First Undergraduate Students Publish as First Authors in ISSCC! 首次大陆本科生发表一作ISSCC

The paper "9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined‑SAR ADC with Continuous‑Time SAR‑Assisted Detect‑and‑Skip and Open‑then‑Close Correlated Level Shifting" has been selected as the highlight paper of the session. Cheers!

Congrats to Siyuan Ye, and whole team!

We will present the total 3 papers in ISSCC 2024 (2024/2/18-2024/2/24). We welcome you to join us and look forward to meeting you in San Francisco.

阅读更多有关 ISSCC 2024 Highlight Paper! 课题组斩获ISSCC 2024亮点论文

Our paper, A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology was presented at ESSCIRC 2023!

The paper is presented by Xinhang Xu! Many congrats to the productive and creative student!  阅读更多有关 ESCRIC 2023 Presented!