Our ISSCC 2023 paper of "A 7.9 fJ/conversion-Step and 37.12 aFrms pipelined-SAR capacitance-to-digital converter with kT/C noise cancellation and incomplete-settling based correlated level shifting" has been selected as the 2023 IEEE International Solid-State Circuits Conference (ISSCC) The Ananthan Chandrakasan Award for Distinguished-Technical Paper. Congrats to Jihang Gao and the whole team! 

The work was designed by Jihang Gao, and Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, and Yunhung Gao are involved in the discussion and technical support. Thanks Prof. Huang for all the resources and support. 

• [2023.ISSCC].23.1 A 7.9fJ/Conversion‑Step and 37.12aFrms Pipelined‑SAR Capacitance‑to‑Digital Converter with kT/C Noise Cancellation and Incomplete‑Settling‑Based Correlated Level Shifting
  • Jihang Gao, Linxiao Shen*(Corresponding), Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Le Ye, Ru Huang
  • 2023 IEEE International Solid‑ State Circuits Conference (ISSCC), 2023

北京大学沈林晓课题组的论文《A 7.9 fJ/conversion-Step and 37.12 aFrms pipelined-SAR capacitance-to-digital converter with kT/C noise cancellation and incomplete-settling based correlated level shifting》获得ISSCC年度最佳论文奖（The Ananthan Chandrakasan Award for Distinguished-Technical Paper）。恭喜文章第一作者高继航，和整个团队！该奖项是IEEE ISSCC顶会最高奖（1/198），每年仅颁发一例。

该工作由文章一作高继航（博士生导师：沈林晓）设计、测试和宣讲发表，感谢团队成员叶思源、李杰、许欣航、崔佳佳和Yunhung Gao讨论。感谢黄如院士和北京大学集成电路学院对本工作的支持！