Analog layout design is still primarily reliant on manual efforts. Current fully automated workflows are unable to meet the expectations for flexible customization and are incompatible with existing manual workflows. For both performance and productivity, interactive layout editing has the ability to bridge the gap between manual and automated flows. We present an interactive layout editing system in this study that includes well-defined commands for both placement and routing customization. This is a pioneering work that provides a holistic study on the interactive design methodology for analog layouts and its capability of speeding up design closure. Our framework comes up with instant placement legalization and routing adjustment mechanism for rapid layout update and modification. The framework is capable of handling realtime user interaction and improving the performance of fully automated layout generators verified by post-layout simulation on real-world analog designs. Experimental results demonstrate the performance enhancement on real-world analog designs with only a few editing commands. As examples, on the low-dropout regulator, our framework can reduce the overshot down and up voltage to nearly 1=3 of layout generated by automation tool with two editing commands, and on the operational transconductance amplifier, it achieves 33:5% better common mode rejection ratio with only one command.

This paper presents a hybrid 4th-order delta-sigma modulator (DSM). It combines a continuous-time (CT) loop filter and a discrete-time (DT) passive 2nd-order noise-shaping SAR (NSSAR). Since the 2nd-order NS-SAR is robust against PVT variation, the stability of this 4th-order DSM is similar to that of a 2nd-order CT-DSM. The CT loop filter is based on single-amplifier bi-quad (SAB) structure. As a result, only one OTA is used to achieve 4th-order noise shaping, leading to a high power efficiency. Moreover, this work implements both excess loop delay (ELD) compensation and an input feedforward path inside the NS-SAR in the charge domain, further reducing the circuit complexity and the OTA power. Overall, this work achieves 81 dB SNDR over 12.5 MHz with 3.7 mW power, leading to a Schreier FoM of 176 dB.

High-precision large dynamic-range (DR) current-sensing front-ends are widely used in biomedical applications, such as patch-clamp, molecular concentration detection, and gene sequencing. The new gene sequencers require low-noise analog front-ends capable of sensing large DR current (>100 dB) down to sub-pA-level. At this level of precision, oversampled data converters are usually used. However, given the limited oversampling ratio in high throughput applications, it is very challenging to achieve a sub-pA-level sensitivity and >100dB DR within the limited area and energy budgets [1]. In [2], a 140dB DR is achieved using a multi-bit delta-sigma modulator (DSM), but the power consumption is over 1mW and the current sensitivity is limited to 6.3pA. An hourglass ADC achieving a 100fA sensitivity and 140dB DR is presented in [3], but is limited by conversion rate and relatively high power consumption (295μW). For a 100Hz bandwidth, its noise floor increases to 18pA.