Analog layout design is still primarily reliant on manual efforts. Current fully automated workflows are unable to meet the expectations for flexible customization and are incompatible with existing manual workflows. For both performance and productivity, interactive layout editing has the ability to bridge the gap between manual and automated flows. We present an interactive layout editing system in this study that includes well-defined commands for both placement and routing customization. This is a pioneering work that provides a holistic study on the interactive design methodology for analog layouts and its capability of speeding up design closure. Our framework comes up with instant placement legalization and routing adjustment mechanism for rapid layout update and modification. The framework is capable of handling realtime user interaction and improving the performance of fully automated layout generators verified by post-layout simulation on real-world analog designs. Experimental results demonstrate the performance enhancement on real-world analog designs with only a few editing commands. As examples, on the low-dropout regulator, our framework can reduce the overshot down and up voltage to nearly 1=3 of layout generated by automation tool with two editing commands, and on the operational transconductance amplifier, it achieves 33:5% better common mode rejection ratio with only one command.

This paper presents a hybrid 4th-order delta-sigma modulator (DSM). It combines a continuous-time (CT) loop filter and a discrete-time (DT) passive 2nd-order noise-shaping SAR (NSSAR). Since the 2nd-order NS-SAR is robust against PVT variation, the stability of this 4th-order DSM is similar to that of a 2nd-order CT-DSM. The CT loop filter is based on single-amplifier bi-quad (SAB) structure. As a result, only one OTA is used to achieve 4th-order noise shaping, leading to a high power efficiency. Moreover, this work implements both excess loop delay (ELD) compensation and an input feedforward path inside the NS-SAR in the charge domain, further reducing the circuit complexity and the OTA power. Overall, this work achieves 81 dB SNDR over 12.5 MHz with 3.7 mW power, leading to a Schreier FoM of 176 dB.

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

The Noise-Shaping (NS) SAR is an attractive new ADC architecture that emerged in the last decade. It combines the advantages of the SAR and the DSM architectures. NS SAR shows excellent potential for high efficiency and low cost, and is highly suited to process scaling. This paper gives an overview of the history of NS-SAR, reviews the fundamentals challenges, and summarizes the latest developments, including advanced loop filtering techniques, DAC mismatch mitigation, kT/C mitigation, and bandwidth boosting. A comprehensive comparison of the state-of-the-art NS-SAR ADCs is provided, and conclusions are derived.

This work introduces a second-order voltage-controlled oscillator (VCO)-based continuous-time delta-sigma modulator (CTDSM) that incorporates a distributed-input VCO as the second-stage integrator and quantizer. The distributed-input VCO topology virtually eliminates the VCO's voltage-to-frequency (V-F) parasitic pole. One of the key ideas of this article is to demonstrate the use of a capacitive-π network in the modulator's loop filter to break the constraint between the size of the modulator's inner capacitive digital-to-analog converter (DAC) and the factor by which the front-end Gm-C integrator is impedance scaled. This, in turn, helps to significantly reduce both analog and digital powers. The prototype chip has been fabricated in a 40-nm CMOS process. Despite not using any DAC calibration or explicit dynamic element matching (DEM) circuits, the worst case spurious-free dynamic range (SFDR) is -82 dBc across the signal bandwidth. The fabricated CTDSM achieves a 71.8-dB signal-to-noise-and-distortion ratio (SNDR) and a 74.5-dB dynamic range (DR) in a 10-MHz bandwidth at 655 MS/s, yielding an SNDR-based Walden figure of merit (FoM) of 45.6 fJ/step, an SNDR-based Schreier FoM of 167.2 dB, and a DR-based Schreier FoM of 169.9 dB.

This work presents an ultra-low-power software-defined always-on wake-up system to drastically decrease the system power of Internet of Things (IoTs) devices, which usually operate in random-sparse-event (RSE) scenarios. It mainly thanks to a clock-free time-shielding level-crossing ADC (TS-LCADC), software-defined clock-free multi-function detectors, and an asynchronous pipelined event-driven architecture. First, by quantifying RSE noisy signals with clock-free adaptive sampling in a signal-noise-rejecting manner, the proposed TS-LCADC reduces number of sampling points and power, and consumes only 41 nW when on-call waiting for IoT events. Second, the proposed clock-free multi-function detectors with offline and online programmability are able to character the signal features of versatile IoTs events and allow versatile and dynamic wake-up functions. Third, the proposed asynchronous pipelined event-driven architecture minimizes the system activity and thus power, because a power-hungry high-performance system (HPS) is only woken up when a detected parameter crosses its corresponding threshold. As such, the long-term average power (LTA-power) is dominated by the always-on circuits in RSE scenarios. The measurement results achieve 71–75 nW for three typical applications, i.e., heart rate, epilepsy, and keyword envelope detection. The LTA power is only 57 nW when waiting for RSE events, which is 30 $\times $ lower than a prior general-purpose wake-up chip. Compared with other works of dedicated voice and acoustic wake-up functions, this work consumes 2 $\times $ and 17 $\times $ less power, respectively, while featuring 16 $\times $ higher signal bandwidth and a broader versatility.

This article presents an adaptive zoom-capacitance-to-digital converter (CDC)-based CMOS humidity sensor. The humidity sensor is realized by means of two differential capacitors whose dielectrics are sensitive to humidity. The sensing capacitors are interfaced with a zoom CDC, which consists of a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 3rd-order delta–sigma modulator ( $Δ Σ \textM$ ). The SAR ADC eliminates the influence of the baseline capacitance to reduce the input range of the $Δ Σ \textM$ . To improve the energy efficiency of the CDC across the full input range, a power-aware floating inverter amplifier (FIA) array is proposed, which is configured based on the conversion results of the SAR logic. In addition, an adaptive range-shift (ARS) zoom CDC is proposed to: 1) resist off-chip parasitics and interference and 2) allow low redundancy and a more energy-efficient FIA-based comparator, thus reducing power consumption. The proposed CMOS humidity sensor is implemented in a 0.11- $μ \textm$ CMOS process. Measurement results show a capacitance resolution of 17.9 aF and an effective number of bits (ENOB) of 14.0 within a conversion time of 1.01 ms. The proposed humidity sensor consumes 1.5 $μ \textW$ of power and exhibits a 0.0094 % relative humidity (RH) resolution and a ±1.5 %RH peak-to-peak accuracy (3 $\sigma $ error of 5.5 %RH) among 12 chips from 20 to 85 %RH, and it achieves a figure of merit (FoM) of 0.135 pJ $\cdot $ %RH2, which is more than six times better than the state of the art.

This article presents a 148-nW always-on wake-up system that drastically reduces the system power consumption of Internet of Things (IoT) sensor nodes while oftentimes operating in random-sparse-event (RSE) scenarios. To significantly reduce the long-term average (LTA) power consumption and realize multiapplication and intelligent event detection, three techniques are proposed: 1) In a three-stage pipelined event-driven architecture, a frame generator and a convolutional neural network intelligent inference engine (CNN IIE) in stage III are event-driven by the preliminary detectors in stage II, and the detectors are triggered by a level-crossing (LC) analog-to-digital converter (ADC), i.e., stage I, dramatically reducing the overall power consumption. 2) The clock-free pulse-based instant rate of change (IROC) feature extractor directly processes the asynchronous pulses of the LC-ADC outputs in the temporal domain instead of utilizing a conventional power-hungry frequency-domain method. 3) A reconfigurable IROC, the frame generator, and the CNN IIE provide adaptive intelligence for various IoT events, enhancing the accuracy of multipurpose detection with ultralow power. We demonstrate two artificial intelligence IoT (AIoT) applications at 0.6-V VDD. For electrocardiogram (ECG) recognition, one example works at a typical event rate (ER) of  4800/h, with an active power of 1.68 $μ \textW$ and a precision of up to 99%; the other is used for keyword spotting (KWS), where the chip achieves 378 nW at  720/h ER and 94% accuracy. The LTA power is bounded to 148 nW, while the event-driven chip is on call and waiting for events; this chip dominates the AIoT device battery life in RSE scenarios.

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only 107 μW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)-ΔΣ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts' counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented to enable a highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40-nm CMOS, the prototype readout achieves 78-dB SNDR in 10-kHz bandwidth, consuming 4.68 μW and 0.025-mm2 active area. With 172-dB Schreier figure of merit, its efficiency advances the state-of-the-art VCO-based readouts by 50×.

This article presents an incremental two-step capacitance-to-digital converter (CDC) with a time-domain ΔΣ modulator (TDΔΣM). Unlike the classic two-step CDCs, this work replaces the operational transconductance amplifier (OTA)-based active-RC integrator by a voltage-controlled oscillator (VCO)-based integrator, which is mostly digital and low-power. Featuring the infinite dc gain and intrinsic quantization in phase domain, this TDΔΣM enables a CDC design achieving 76-dB SNDR while requiring only a first-order loop, and a low oversampling ratio (OSR) of 15. Fabricated in 40-nm CMOS technology, the prototype CDC achieves a resolution of 0.29 fF while dissipating only 0.083 nJ/conversion, which improves the energy efficiency by over two times comparing to the similar performance designs.

As any analog-to-digital converter (ADC) with a front-end sample-and-hold (S/H) circuit, successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise ratio (SNR) challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor size has to be sufficiently large, leading to a great burden for the design of the ADC input driver and reference buffer. This article presents an SAR ADC with a kT/C noise-cancellation technique. It enables the substantial reduction of ADC input capacitor size but without the large kT/C noise penalty. It greatly relaxes the requirement for ADC input driver and reference buffer. Built in 40-nm CMOS, a prototype 13-bit ADC has only 240-fF input capacitance and occupies a small area of 0.005 mm2. Operating at 40 MS/s, it achieves a 69-dB signal-to-noise-and-distortion ratio (SNDR) across the Nyquist frequency band while consuming 591 μW of power.

This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) ΔΣ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply.

This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting gm/ID and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.

This letter presents a high-speed closed-loop capacitive-input voltage controlled oscillators (VCO)-based continuous-time delta sigma modulator (CTDSM) using a novel fully differential VCO topology whose parasitic pole is inherently located at a very high frequency, regardless of the number of inverters in the ring VCO. The mitigation of the parasitic pole is achieved by splitting the VCO's input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO's input capacitance. A single pair of pseudo-resistors is used for providing dc negative feedback in the CTDSM. The prototype first-order 63-stage VCO-based CTDSM is fabricated in 40-nm CMOS and occupies a core area of 0.02 mm2 while achieving 63.1-dB dynamic range in 480 kHz-20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors' best knowledge, this is also the first work to demonstrate the capacitive input in a high-speed CTDSM, without using chopping.

This paper presents a highly power-efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves six-time current reuse, thereby significantly boosting the transconductance and lowering noise but without increasing the current consumption. A novel biasing scheme is devised to ensure robust operation under 1-V supply. A prototype in 180-nm CMOS has 5.5-μVrms noise within 10-kHz BW while consuming only 0.25-μW power, leading to a noise efficiency factor of 1.07, which is the best among reported amplifiers.