科研成果 by Year: 2019

2019
Xu B, Lin Y, TANG X, Li S, Shen L, Sun N, Pan DZ. WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout, in 2019 56th ACM/IEEE Design Automation Conference (DAC).; 2019:1-6.Abstract
In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS layout automation tools comes to a large extent from the difficulty in comprehending and incorporating designer expertise. To mimic the behavior of experienced designers in well generation, we propose a generative adversarial network (GAN) guided well generation framework with a post-refinement stage leveraging the previous high-quality manually-crafted layouts. Guiding regions for wells are first created by a trained GAN model, after which the well generation results are legalized through post-refinement to satisfy design rules. Experimental results show that the proposed technique is able to generate wells close to manual designs with comparable post-layout circuit performance.
Mukherjee A, Gandara M, Xu B, Li S, Shen L, TANG X, Pan D, Sun N. A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $ΔΣ$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO. IEEE Solid-State Circuits Letters. 2019;2:1-4.Abstract
This letter presents a high-speed closed-loop capacitive-input voltage controlled oscillators (VCO)-based continuous-time delta sigma modulator (CTDSM) using a novel fully differential VCO topology whose parasitic pole is inherently located at a very high frequency, regardless of the number of inverters in the ring VCO. The mitigation of the parasitic pole is achieved by splitting the VCO's input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO's input capacitance. A single pair of pseudo-resistors is used for providing dc negative feedback in the CTDSM. The prototype first-order 63-stage VCO-based CTDSM is fabricated in 40-nm CMOS and occupies a core area of 0.02 mm2 while achieving 63.1-dB dynamic range in 480 kHz-20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors' best knowledge, this is also the first work to demonstrate the capacitive input in a high-speed CTDSM, without using chopping.
Shen L, Mukherjee A, Li S, TANG X, Lu N, Sun N. A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF, in 2019 Symposium on VLSI Circuits.; 2019:C144-C145.
TANG X, Li S, Shen L, Zhao W, Yang X, Williams R, Liu J, Tan Z, Hall N, Sun N. 18.2 A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter, in 2019 IEEE International Solid- State Circuits Conference - (ISSCC).; 2019:296-297.
Shen L, Shen Y, TANG X, Hsu C-K, Shi W, Li S, Zhao W, Mukherjee A, Sun N. 3.4 A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor, in 2019 IEEE International Solid- State Circuits Conference - (ISSCC).; 2019:64-66.