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Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer

Citation:

Seidel K, Lehninger D, Hoffmann R, Ali T, Lederer M, Revello R, Mertens K, Biederma K. Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) [Internet]. 2022:355-356.
Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer

摘要:

In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.

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