<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>10</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Konrad Seidel</style></author><author><style face="normal" font="default" size="100%">David Lehninger</style></author><author><style face="normal" font="default" size="100%">Raik Hoffmann</style></author><author><style face="normal" font="default" size="100%">Tarek Ali</style></author><author><style face="normal" font="default" size="100%">Maximilian Lederer</style></author><author><style face="normal" font="default" size="100%">Ricardo Revello</style></author><author><style face="normal" font="default" size="100%">Konstantin Mertens</style></author><author><style face="normal" font="default" size="100%">Kati Biederma</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer</style></title><secondary-title><style face="normal" font="default" size="100%">2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2022</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://ieeexplore.ieee.org/abstract/document/9830141</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">IEEE</style></publisher><pub-location><style face="normal" font="default" size="100%">Honolulu, HI, USA</style></pub-location><pages><style face="normal" font="default" size="100%">355-356</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.</style></abstract></record></records></xml>