@proceedings {37408,
	title = {Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer},
	journal = {2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)},
	year = {2022},
	pages = {355-356},
	publisher = {IEEE},
	address = {Honolulu, HI, USA},
	abstract = {In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.},
	url = {https://ieeexplore.ieee.org/abstract/document/9830141},
	author = {Konrad Seidel and David Lehninger and Raik Hoffmann and Tarek Ali and Maximilian Lederer and Ricardo Revello and Konstantin Mertens and Kati Biederma}
}
