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Publications

2020
Wu, Xiao, Yufei Ma, and Zhongfeng Wang. “Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA.” IEEE International System-on-Chip Conference (SOCC), 2020. Links
Ma, Yufei, Yuan Du, Li Du, Jun Lin, and Zhongfeng Wang. “In-Memory Computing: The Next-Generation AI Computing Paradigm.” ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020. Links
Chen, Zhiyuan, Yufei Ma*, and Zhongfeng Wang. “Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks.” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2020. Links
Krishnan, Gokul, Yufei Ma, and Yu Cao. “Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks.” IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020. Links
Ma*, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 39, no. 2 (2020): 424 - 437. Links
Ma*, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “Performance Modeling for CNN Inference Accelerators on FPGA.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 39, no. 4 (2020): 843 - 856. Links
2019
Venkataramanaiah, Shreyas Kolala, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao, and Jae-Sun Seo. “Automatic Compiler Based FPGA Accelerator for CNN Training.” IEEE International Conference on Field Programmable Logic and Applications (FPL), 2019. Links
Du*, Xiaocong, Zheng Li, Yufei Ma*, and Yu Cao. “Efficient Network Construction Through Structural Plasticity.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) 9, no. 3 (2019): 453 - 464. Links
2018
Ma*, Yufei, Naveen Suda, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.” Integration, the VLSI Journal (2018). Links
Ma, Yufei, Tu Zheng, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs.” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018. Links
Ma*, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI) 26, no. 7 (2018): 1354 - 1367. Links
2017
Ma, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “An Automatic RTL Compiler for High-Throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks.” IEEE International Conference on Field Programmable Logic and Applications (FPL), 2017. Links
Ma, Yufei, Minkyu Kim, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “End-to-End Scalable FPGA Accelerator for Deep Residual Networks.” IEEE International Symposium on Circuits and Systems (ISCAS), 2017. Links
Ma, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2017. Links
2016
Ma, Yufei, Naveen Suda, Yu Cao, Jae-Sun Seo, and Sarma Vrudhula. “Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.” IEEE International Conference on Field Programmable Logic and Applications (FPL), 2016. Links
Suda, Naveen, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma Vrudhula, Jae-Sun Seo, and Yu Cao. “Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2016. Links
2015
Ma, Yufei, Minkyu Kim, Yu Cao, Jae-Sun Seo, and Sarma Vrudhula. “Energy-Efficient Reconstruction of Compressively Sensed Bioelectrical Signals withStochastic Computing Circuits.” IEEE International Conference on Computer Design (ICCD), 2015. Links

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