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科研成果 by Type: Conference Proceedings

2024
Dong, Yanchi, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, et al.. “A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup.” IEEE Symposium on VLSI Technology and Circuits (VLSI-C), 2024. Links
Chen, Zhiyuan, Yufei Ma*, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, and Ru HUANG. “An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology.” ACM/IEEE Design Automation Conference (DAC), 2024.
Qiu, Yikan, Yufei Ma*, Meng Wu, Yifan Jia, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, and Ru HUANG. “Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.” IEEE Custom Integrated Circuits Conference (CICC), 2024. Links
Wu, Meng, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, et al.. “S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.” IEEE Custom Integrated Circuits Conference (CICC), 2024. Links
Liu#, Ying, Yufei Ma#, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, et al.. “A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflowand Sparsity-Adaptive In-Memory Computing.” IEEE International Solid-State Circuits Conference (ISSCC 2024), 2024. Links
2023
Liu, Ying, Zhiyuan Chen, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Qijun Wang, et al.. “A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.” IEEE Custom Integrated Circuits Conference (CICC), 2023. Links
Jing, Yiqi, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, and Tianyu Jia. “DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.” IEEE/ACM Int. Symp. on Low Power Electronics and Design (ISLPED), 2023. Links
Dong, Yanchi, Tianyu Jia*, .., Yufei Ma, Yun Liang, Le Ye*, and Ru HUANG. “A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.” ACM/IEEE Design Automation Conference (DAC), 2023. Links
Chen, Peiyu, Meng Wu, Yufei Ma*, Le Ye*, and Ru HUANG. “RIMAC: An Array-level ADC/DAC-free ReRAM-based In-MemoryDNN Processor with Analog Cache and Computation.” Asia and South Pacific Design Automation Conference (ASP-DAC), 2023. Links
Chen#, Peiyu, Meng Wu#, ..., Yufei Ma*, Le Ye*, and Ru HUANG. “A 22-nm Delta-Sigma Computing-In-Memory (ΔΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.” IEEE International Solid-State Circuits Conference (ISSCC 2023), 2023. Links
2022
Qiu, Yikan, Yufei Ma*, Wentao Zhao, Meng Wu, Le Ye*, and Ru HUANG. “DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2022. Links
2020
Ma, Yufei, Yuan Du, Li Du, Jun Lin, and Zhongfeng Wang. “In-Memory Computing: The Next-Generation AI Computing Paradigm.” ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020. Links
Krishnan, Gokul, Yufei Ma, and Yu Cao. “Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks.” IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020. Links
Wu, Xiao, Yufei Ma, and Zhongfeng Wang. “Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA.” IEEE International System-on-Chip Conference (SOCC), 2020. Links
Zhang, Hui, Wei Wu, Yufei Ma, and Zhongfeng Wang. “Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA.” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020. Links
Wen, Jiayu, Yufei Ma, and Zhongfeng Wang. “An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference.” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020. Links
Chen, Zhiyuan, Yufei Ma*, and Zhongfeng Wang. “Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks.” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2020. Links
2019
Venkataramanaiah, Shreyas Kolala, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao, and Jae-Sun Seo. “Automatic Compiler Based FPGA Accelerator for CNN Training.” IEEE International Conference on Field Programmable Logic and Applications (FPL), 2019. Links
2018
Ma, Yufei, Tu Zheng, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs.” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018. Links
2017
Ma, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “An Automatic RTL Compiler for High-Throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks.” IEEE International Conference on Field Programmable Logic and Applications (FPL), 2017. Links

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