Publications

2024

Qiu, Yikan, Yufei Ma*, Meng Wu, Yifan Jia, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, and Ru HUANG. “Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.” IEEE Custom Integrated Circuits Conference (CICC), 2024. Links

Wu, Meng, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, et al.. “S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.” IEEE Custom Integrated Circuits Conference (CICC), 2024. Links

Ma#*, Yufei, Yikan Qiu#, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, and Ru HUANG. “DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network.” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2024). Links

Liu, Ying, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang*, Ru HUANG, Le Ye, and Yufei Ma*. “Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network.” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2024). Links

Liu#, Ying, Yufei Ma#, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, et al.. “A 22nm 0.26nW/Synapse Spike-Driven Spiking NeuralNetwork Processing Unit Using Time-Step-First Dataflowand Sparsity-Adaptive In-Memory Computing.” IEEE International Solid-State Circuits Conference (ISSCC 2024), 2024. Links

2023

Chen#, Peiyu, Meng Wu#, ..., Yufei Ma*, Le Ye*, and Ru HUANG. “A 22-nm Delta-Sigma Computing-In-Memory (ΔΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.” IEEE International Solid-State Circuits Conference (ISSCC 2023), 2023. Links

Dong, Yanchi, Tianyu Jia*, .., Yufei Ma, Yun Liang, Le Ye*, and Ru HUANG. “A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.” ACM/IEEE Design Automation Conference (DAC), 2023. Links

Liu, Ying, Zhiyuan Chen, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Qijun Wang, et al.. “A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.” IEEE Custom Integrated Circuits Conference (CICC), 2023. Links

Liu#, Ying, Yufei Ma#*, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru HUANG, and Le Ye*. “An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2023). Links

Jing, Yiqi, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, and Tianyu Jia. “DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.” IEEE/ACM Int. Symp. on Low Power Electronics and Design (ISLPED), 2023. Links

Chen, Peiyu, Meng Wu, Yufei Ma*, Le Ye*, and Ru HUANG. “RIMAC: An Array-level ADC/DAC-free ReRAM-based In-MemoryDNN Processor with Analog Cache and Computation.” Asia and South Pacific Design Automation Conference (ASP-DAC), 2023. Links

2022

Qiu, Yikan, Yufei Ma*, Wentao Zhao, Meng Wu, Le Ye*, and Ru HUANG. “DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.” IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), 2022. Links

Wu, Xiao, Yufei Ma*, Meiqi Wang, and Zhongfeng Wang*. “A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs.” IEEE Transactions on Circuits and Systems I: Regular Paper (TCAS-I) (2022). Links

Chen, Zhiyuan, Yufei Ma*, and Zhongfeng Wang*. “Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs.” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022). Links