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Yufei Ma
/ 马宇飞
Assistant Professor
Institute for Artificial Intelligence
School of Integrated Circuits
Peking University
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Email:
yufei.ma@pku.edu.cn
No.5 Yiheyuan Road, Haidian District, Beijing 100871, P.R.China
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科研成果 by Type: 期刊论文
2024
Chen, Peiyu, Meng Wu, Wentao Zhao, Yufei Ma, Tianyu Jia*, and Le Ye
. “
A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations
.”
IEEE Solid-State Circuits Letters
(2024).
Links
Liu, Ying, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang*, Ru HUANG, Le Ye, and Yufei Ma*
. “
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network
.”
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
(2024).
Links
Ma#*, Yufei, Yikan Qiu#, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, and Ru HUANG
. “
DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network
.”
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
(2024).
Links
2023
Liu#, Ying, Yufei Ma#*, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru HUANG, and Le Ye*
. “
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique
.”
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
(2023).
Links
2022
Chen, Zhiyuan, Yufei Ma*, and Zhongfeng Wang*
. “
Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs
.”
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
(2022).
Links
Wu, Xiao, Yufei Ma*, Meiqi Wang, and Zhongfeng Wang*
. “
A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs
.”
IEEE Transactions on Circuits and Systems I: Regular Paper (TCAS-I)
(2022).
Links
2020
Ma*, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo
. “
Performance Modeling for CNN Inference Accelerators on FPGA
.”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
39, no. 4 (2020): 843 - 856.
Links
Ma*, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo
. “
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators
.”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
39, no. 2 (2020): 424 - 437.
Links
2019
Du*, Xiaocong, Zheng Li, Yufei Ma*, and Yu Cao
. “
Efficient Network Construction Through Structural Plasticity
.”
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
9, no. 3 (2019): 453 - 464.
Links
2018
Ma*, Yufei, Naveen Suda, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo
. “
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler
.”
Integration, the VLSI Journal
(2018).
Links
Ma*, Yufei, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo
. “
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
.”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
26, no. 7 (2018): 1354 - 1367.
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Types
Conference Proceedings
(26)
期刊论文
(11)
Summary
2024
(9)
2023
(6)
2022
(3)
2020
(8)
2019
(2)
2018
(3)
2017
(3)
2016
(2)
2015
(1)
* Corresponding Author
# Co-First Author