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Publication

* Corresponding Author,     # Co-First Author

2025

  1. [CVPR] Zhiyuan Chen, Keyi Li, Yifan Jia, Le Ye, and Yufei Ma*. "Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition," in IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 2025.

  2. [DAC] Guoxiang Li, Runnan Xu, Ruohang Xu, Yikan Qiu, Renati Tuerhong, Muhan Zhang, Le Ye, and Yufei Ma*. "3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs," in IEEE/ACM Design Automation Conference (DAC), 2025.

  3. [DAC] Wentao Zhao, Boya Lv, Meng Wu, Peiyu Chen, Fengyun Yan, Yufei Ma, Tianyu Jia, Ru Huang, and Le Ye. "3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference," in IEEE/ACM Design Automation Conference (DAC), 2025.

  4. [JSSC] Peiyu Chen#, Wentao Zhao#, Meng Wu, Linxiao Shen, Tianyu Jia, Ru Huang, Le Ye*, and Yufei Ma*. "A 22-nm Delta–Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing," in IEEE Journal of Solid-State Circuits (JSSC), 2025. Link

  5. [ISSCC] Ying Liu, Jie Li, Qining Zhang, Tianhao Zhao, Chenhao Shi, Ninghui Shang, Peiyu Chen, Xiaohuan Ge, Yufei Ma, Linxiao Shen, Zhixuan Wang, Ru Huang, Le Ye. "13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction," in IEEE International Solid-State Circuits Conference (ISSCC), 2025. Link

2024

  1. [TCAS-I] Yufei Ma*#, Yikan Qiu#, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, and Ru Huang. "DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network," in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024. Link

  2. [TCAS-I] Ying Liu, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang*, Ru Huang, Le Ye, and Yufei Ma*. "Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network," in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024. Link

  3. [ISSCC] Ying Liu#, Yufei Ma#, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, Tianyu Jia, Le Ye, Zhixuan Wang, and Ru Huang. "30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing," in IEEE International Solid-State Circuits Conference (ISSCC), 2024. Link

  4. [DAC] Zhiyuan Chen, Yufei Ma*, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, and Ru Huang. "An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology," in IEEE/ACM Design Automation Conference (DAC), 2024. Link

  5. [DAC] Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Le Ye, and Tianyu Jia. "AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration," in IEEE/ACM Design Automation Conference (DAC), 2024. Link

  6. [CICC] Yikan Qiu, Yufei Ma*, Meng Wu, Yifan Jia, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, and Ru Huang. "Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow," in IEEE Custom Integrated Circuits Conference (CICC), 2024. Link

  7. [CICC] Meng Wu, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, Yufei Ma, Ru Huang, Tianyu Jia, and Le Ye. "S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications," in IEEE Custom Integrated Circuits Conference (CICC), 2024. Link

  8. [VLSI-C] Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye, Tianyu Jia. "A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup," in IEEE Symposium on VLSI Technology and Circuits (VLSI-C), 2024. Link

  9. [SSC-L] Peiyu Chen, Meng Wu, Wentao Zhao, Yufei Ma, Tianyu Jia, and Le Ye. "A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations," in IEEE Solid-State Circuits Letters (SSC-L), 2024. Link

2023

  1. [ISSCC] Peiyu Chen#, Meng Wu#, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma*, Le Ye*, and Ru Huang. "7.8 A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing," in IEEE International Solid-State Circuits Conference (ISSCC), 2023. Link

  2. [TCAS-I] Ying Liu#, Yufei Ma#*, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru Huang, and Le Ye*. "An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique," in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2023, Highlight of 2023 August Issue. Link

  3. [CICC] Ying Liu, Zhiyuan Chen, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Qijun Wang, Ning Zhang, Tianyu Jia, Yufei Ma*, Le Ye*, and Ru Huang. "A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology," in IEEE Custom Integrated Circuits Conference (CICC), 2023. Link

  4. [ASP-DAC] Peiyu Chen, Meng Wu, Yufei Ma*, Le Ye*, and Ru Huang. "RIMAC: An Array-level ADC/DAC-free ReRAM-based In-Memory DNN Processor with Analog Cache and Computation," in Asia and South Pacific Design Automation Conference (ASP-DAC), 2023. Link

  5. [DAC] Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, and Ru Huang. "A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware," in ACM/IEEE Design Automation Conference (DAC), 2023. Link

  6. [ISLPED] Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, and Tianyu Jia. "DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler," in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023. Link

2022

  1. [ICCAD] Yikan Qiu, Yufei Ma*, Wentao Zhao, Meng Wu, Le Ye*, and Ru Huang. "DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks," in IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022. Link

  2. [TCAS-I] Zhiyuan Chen, Yufei Ma*, and Zhongfeng Wang*. "Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs," in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2022. Link

  3. [TCAS-I] Xiao Wu, Yufei Ma*, Meiqi Wang, and Zhongfeng Wang*. "A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs," in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2022. Link

2020

  1. [ICCAD] Zhiyuan Chen, Yufei Ma*, and Zhongfeng Wang. "Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks," in IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020. Link

  2. [SOCC] Xiao Wu, Yufei Ma, and Zhongfeng Wang. "Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA," in IEEE International System-on-Chip Conference (SOCC), 2020. Link

  3. [GLSVLSI] Yufei Ma, Yuan Du, Li Du, Jun Lin, and Zhongfeng Wang. "In-Memory Computing: The Next-Generation AI Computing Paradigm," in Great Lakes Symposium on VLSI(GLSVLSI), 2020. Link

  4. [TCAD] Yufei Ma*, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020. Link

  5. [TCAD] Yufei Ma*, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "Performance Modeling for CNN Inference Accelerators on FPGA," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020. Link

  6. [ICSICT] Gokul Krishnan, Yufei Ma, and Yu Cao. "Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks," in IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020. Link

2019 and Before

  1. [JETCAS] Xiaocong Du*, Zheng Li, Yufei Ma*, and Yu Cao. "Efficient Network Construction Through Structural Plasticity," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2019. Link

  2. [FPL] Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, and Yu Cao. "Automatic Compiler Based FPGA Accelerator for CNN Training," in International Conference on Field Programmable Logic and Applications (FPL), 2019. Link

  3. [Integration] Yufei Ma*, Naveen Suda, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler," in Integration, the VLSI Journal, 2018. Link

  4. [ICCAD] Yufei Ma, Tu Zheng, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018. Link

  5. [TVLSI] Yufei Ma*, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA," in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018. Link

  6. [FPGA] Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks," in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2017. Link

  7. [FPL] Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "An Automatic RTL Compiler for High-Throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks," in IEEE International Conference on Field Programmable Logic and Applications (FPL), 2017. Link

  8. [ISCAS] Yufei Ma, Minkyu Kim, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. "End-to-End Scalable FPGA Accelerator for Deep Residual Networks," in IEEE International Symposium on Circuits and Systems (ISCAS), 2017. Link

  9. [FPL] Yufei Ma, Naveen Suda, Yu Cao, Jae-Sun Seo, and Sarma Vrudhula. "Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA," in IEEE International Conference on Field Programmable Logic and Applications (FPL), 2017. Link

  10. [FPGA] Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma Vrudhula, Jae-Sun Seo, and Yu Cao. "Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks," in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2016. Link

  11. [ICCD] Yufei Ma, Minkyu Kim, Yu Cao, Jae-Sun Seo, and Sarma Vrudhula. "Energy-Efficient Reconstruction of Compressively Sensed Bioelectrical Signals with Stochastic Computing Circuits," in IEEE International Conference on Computer Design (ICCD), 2015. Link