Recently, hafnium oxide based ferroelectric memories gained great attention due to good scalability, high speed operation, and low power consumption. In contrast to the FRAM concept, the FeFET offers non-destructive read-out. However, the integration of the FeFET into an established CMOS technology entails several challenges. Herein, an 1T1C FeFET with separated transistor (1T) and ferroelectric capacitor (1C) is described and demonstrated. This alternative approach can be integrated into standard process technologies without introducing significant modifications of the front-end-of-line. All important steps starting from the integration of MFM devices into the BEoL through the fabrication and characterization of single 1T1C memory cells with various capacitor area ratios for bit cell tuning up to the initial demonstration of an 8 kbit test-array are covered.
In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.
