ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Ma*, Yufei, Naveen Suda, Yu Cao, Sarma Vrudhula, and Jae-Sun Seo. “ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.” Integration, the VLSI Journal (2018). Copy at http://scholar.pku.edu.cn/yufei.ma/publications/alamo-fpga-acceleration-deep-learning-algorithms-modularized-rtl-compiler