Citation:Tao Y, Cho S-G, Zhang Z. A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm 2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS, in 2019 Symposium on VLSI Circuits. IEEE; 2019:C240–C241.ExportBibTex EndNote Tagged EndNote XML 访问链接