Tang* W, Cho* S-G, Hoang* TT, Botimer J, Zhu WQ, Chang C-C, Lu C-H, Zhu J, Tao Y, Wei T, et al. Arvon: A heterogeneous SiP integrating a 14nm FPGA and two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 interface to provide versatile workload acceleration, in 2023 Symposium on VLSI Circuits. IEEE; 2023:C7-1.

Cai L, Wang J, Yu L, Yan B, Tao Y*, Yang Y*. Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-Based Stepsize Search, in Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). New York, NY, USA: Association for Computing Machinery; 2023:177–183. 访问链接

Zhu* J, Tao* Y, Zhang Z. eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs, in The 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE; 2023. 访问链接

Yu L, Jing Z, Yang Y, Tao Y. Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm, in 2022 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2022:590–594. 访问链接

Tao Y, Choi C. High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder, in 2022 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2022:2057–2061. 访问链接

Tao Y, Zhang Z. Hima: A fast and scalable history-based memory access engine for differentiable neural computer, in MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).; 2021:845–856. 访问链接

Tao Y, Zhang Z. DNC-Aided SCL-Flip Decoding of Polar Codes, in 2021 IEEE Global Communications Conference (GLOBECOM). IEEE; 2021:01–06. 访问链接

Tao Y, Cho S-G, Zhang Z. A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm 2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS, in 2019 Symposium on VLSI Circuits. IEEE; 2019:C240–C241. 访问链接

Attari M, Malkowsky S, Tao Y, Zhang Z, Edfors O, Liu L. A Programmable 16x16 Systolic Array Enhanced ASIP for Massive MIMO, in 2019 IEEE Asilomar Conference on Signals, Systems, and Computers. IEEE; 2019. 访问链接

Tao Y, Wu Q. An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2019:1–5. 访问链接

Park YS, Tao Y, Sun S, Zhang Z. A 4.68 Gb/s belief propagation polar decoder with bit-splitting register file, in 2014 Symposium on VLSI Circuits Digest of Technical Papers. IEEE; 2014:1–2. 访问链接

Park YS, Tao Y, Zhang Z. A 1.15 Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating, in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers. IEEE; 2013:422–423. 访问链接

Chen C-H, Tao Y, Zhang Z. Efficient in situ error detection enabling diverse path coverage, in 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2013:773–776. 访问链接

Tao Y, Park YS, Zhang Z. High-throughput architecture and implementation of regular (2, d c) nonbinary LDPC decoders, in 2012 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2012:2625–2628. 访问链接