Tang* W, Cho* S-G, Hoang* TT, Botimer J, Zhu WQ, Chang C-C, Lu C-H, Zhu J, Tao Y, Wei T, et al. Arvon: A heterogeneous SiP integrating a 14nm FPGA and two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 interface to provide versatile workload acceleration, in 2023 Symposium on VLSI Circuits. IEEE; 2023:C7-1.

Cai L, Yu L, Yue W, Zhu Y, Yang Z, Li Y, Tao Y*, Yang Y*. Integrated Memristor Network for Physiological Signal Processing. Advanced Electronic Materials. 2023:2300021.

Fan A, Fu Y, Tao Y, Jin Z, Han H, Liu H, Zhang Y, Yan B, Yang Y, HUANG R. Hadamard product-based in-memory computing design for floating point neural network training. Neuromorphic Computing and Engineering (NCE) [Internet]. 2023;3(1). 访问链接

Cai L, Wang J, Yu L, Yan B, Tao Y*, Yang Y*. Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-Based Stepsize Search, in Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). New York, NY, USA: Association for Computing Machinery; 2023:177–183. 访问链接

Zhu* J, Tao* Y, Zhang Z. eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs, in The 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE; 2023. 访问链接