Tao Y, Sun S, Zhang Z. Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. IEEE Transactions on Circuits and Systems I: Regular Papers [Internet]. 2019;66:4032–4043. 访问链接

Tao Y, Cho S-G, Zhang Z. A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm 2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS, in 2019 Symposium on VLSI Circuits. IEEE; 2019:C240–C241. 访问链接

Attari M, Malkowsky S, Tao Y, Zhang Z, Edfors O, Liu L. A Programmable 16x16 Systolic Array Enhanced ASIP for Massive MIMO, in 2019 IEEE Asilomar Conference on Signals, Systems, and Computers. IEEE; 2019. 访问链接

Tao Y, Wu Q. An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2019:1–5. 访问链接