<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Tao, Yaoyu</style></author><author><style face="normal" font="default" size="100%">Cho, Sung-Gun</style></author><author><style face="normal" font="default" size="100%">Zhang, Zhengya</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm 2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS</style></title><secondary-title><style face="normal" font="default" size="100%">2019 Symposium on VLSI Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2019</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://ieeexplore.ieee.org/abstract/document/8778009/</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">IEEE</style></publisher><pages><style face="normal" font="default" size="100%">C240–C241</style></pages><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>