One paper introduces a flexible systolic CIM macro (collaborated with Prof. Le Ye), and the other paper shows a heterogeneous CIM-based processor (collaborated with Prof. Yufei Ma).
One 12nm agile-designed SoC is designed with decentralized power management (work done at Harvard), and a 22nm 0.26nW/synapse SNN accelerator will be presented (collaborated with Prof. Le Ye).
