Agile-Designed 12nm Domain-Specific SoC (ISSCC'24, ESSCIRC'22) Reconfigurable Neural CPU (MICRO'20) a DNN Accelerator with Adaptive Clocking (ISSCC'20, JSSC invited) a Instruction-Driven Clocking for GPGPU and CPU (ISSCC'19, ESSCIRC'18, JSSC'20, JSSC'19) a Fully Integrated Buck Regulators with Resonant Switching (VLSI'17, JSSC, A-SSCC'18)
