芯片展/Chip Gallery

I have led several chip tapeout using 12nm or 65nm. The tapeout designs include AI accelerators, CPU, GPU cores, power management circuits. Here are some examples.

Reconfigurable Neural CPU (MICRO'20)

ncpu_die

a

DNN Accelerator with Adaptive Clocking (ISSCC'20, JSSC invited)

dnn_die

a

Instruction-Driven Clocking for GPGPU and CPU (ISSCC'19, ESSCIRC'18, JSSC'20, JSSC'19)gpgpu   arm_cpu

a

Fully Integrated Buck Regulators with Resonant Switching (VLSI'17, JSSC, A-SSCC'18)regulator_die regulator_die2