(* corresponding author; # equal contribution author)
Year 2023
[1] J. Cui, J. Wei*, M. Wang*, Y. Wu, J. Yang, T. Li, J. Yu, H. Yang, X. Yang, J. Wang, X. Liu, D. Ueda, and B. Shen*, “6500-V E-mode active-passivation p-GaN gate HEMT with ultralow dynamic RON,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2023, sec 26-1.
[2] J. Yang, J. Wei*, M. Wang*, M. Nuo, H. Yang, T. Li, J. Yu, X. Yang, Y. Hao, J. Wang, and B. Shen*, “650-V GaN-on-Si power integration platform using virtual-body p-GaN gate HEMT to screen substrate-inudced crosstalk,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2023, sec 9-6.
[3] J. Yang, J. Wei*, M. Wang*, T. Li, J. Yu, J. Wang, and B. Shen*, “Simultaneously achieving large gate swing and enhanced threshold voltage stability in metal/insulator/p-GaN gate HEMT,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2023, sec 9-4.
[4] J. Yang, Y. Wu, M. Nuo, Z. Chen, X. Yang, B. Shen, M. Wang*, and J. Wei*, “Exploitation of hole injection and spreading for dynamic enhancement in p-GaN gate HEMT under room/high temperatures,” in Proc. ISPSD, Hong Kong, China, May 2023, pp. 111-114, doi: 10.1109/ISPSD57135.2023.10147649.
[5] Y. Wu, M. Nuo, J. Yang, Z. Zheng, L. Zhang, K. J. Chen, M. Hua, Y. Hao, X. Yang, B. Shen, M. Wang*, and J. Wei*, “High dynamic stability in enhancement-mode active-passivation p-GaN gate HEMT,” in Proc. ISPSD, Hong Kong, China, May 2023, pp. 378-381, doi: 10.1109/ISPSD57135.2023.10147690.
[6] J. Cui, Y. Wu, J. Yang, J. Yu, T. Li, X. Yang, B. Shen, M. Wang*, and J. Wei*, “Method to study dynamic depletion behaviors in high-voltage (BV = 1.4 kV) p-GaN gate HEMT on sapphire substrate,” in Proc. ISPSD, Hong Kong, China, May 2023, pp. 127-130, doi: 10.1109/ISPSD57135.2023.10147490.
[7] S. Feng, Z. Zheng, Y. Wang, G. Lyu, K. Liu, Y. Cheng, J. Chen, T. Chen, L. Zhang, W. Song, H. Liao, Y. H. Ng, M. Hua, K. Cheng, J. Wei, and K. Chen, "HyFET—A GaN/SiC hybrid field-effect transistor," in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2023, sec 9-2.
[8] J. Chen, T. Chen, Z. Jiang, C. Wang, Z. Zheng, J. Wei, K. J. Chen, and M. Hua, “Switching performance of GaN p-FET-bridge (PFB-) HEMTs studied with mixed-mode TCAD simulation,” in Proc. ISPSD, Hong Kong, China, May 2023, pp. 107-110, doi: 10.1109/ISPSD57135.2023.10147458.
Year 2022
[9] G. Lyu, J. Wei*, Y. H. Ng, Y. Cheng, S. Feng, and K. J. Chen*, “Substrate and trench design for GaN-on-EBUS power IC platform considering output capacitance and isolation between high-side and low-side transistors,” in Proc. ISPSD, Vancouver, BC, Canada, May 2022, pp. 185-188, doi: 10.1109/ISPSD49238.2022.9813683.
[10] H. Xu, Z. Zheng, L. Zhang, J. Sun, S. Yang, J. He, J. Wei, and K. J. Chen, “Dynamic interplays of gate junctions in Schottky-type p-GaN gate power HEMTs during switching operation,” in Proc. ISPSD, Vancouver, BC, Canada, May 2022, pp. 325-328, doi: 10.1109/ISPSD49238.2022.9813627.
Year 2021
[11] G. Lyu, J. Wei*, W. Song, Z. Zheng, L. Zhang, J. Zhang, Y. Cheng, S. Feng, Y. H. Ng, T. Chen, K. Zhong, J. Liu, R. Zeng, and K. J. Chen*, “A GaN power integration platform based on engineered bulk Si substrate with eliminated crosstalk between high-side and low-side HEMTs,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2021, pp. 102-105, doi: 10.1109/IEDM19574.2021.9720505.
Year 2020
[12] (Invited) J. Wei, H. Xu, R. Xie, and K. J. Chen, “Dynamic Vth in p-GaN gate power HEMTs and its impacts upon power switching circuits,” in Proc. ICSICT, Kunming, China, Nov. 2020, pp. 646-649.
[13] J. Wei, M. Zhang, G. Lyu, and K. J. Chen, “Substrate effects in GaN-on-Si integrated bridge circuit and proposal of engineered bulk silicon substrate for GaN power ICs,” in Proc. WiPDA Asia, Osaka, Japan, Sep. 2020, pp. 220-223, doi: 10.1109/WiPDAAsia49671.2020.9360273.
[14] J. Wei, M. Zhang and K. J. Chen, “Design of dual-gate superjunction IGBT towards fully conductivity-modulated bipolar conduction and near-unipolar turn-off,” in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 498-501, doi: 10.1109/ISPSD46842.2020.9170090.
[15] H. Xu#, J. Wei#, R. Xie, Z. Zheng, L. Zhang, and K. J. Chen, “A SPICE-compatible equivalent-circuit model of Schottky type p-GaN gate power HEMTs with dynamic threshold voltage”, in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 325-328, doi: 10.1109/ISPSD46842.2020.9170086.
[16] Z. Zheng, W. Song, L. Zhang, S. Yang, H. Xu, R. Wong, J. Wei*, and K. J. Chen*, “Enhancement-mode GaN p-channel MOSFETs for power integration,” in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 525-528, doi: 10.1109/ISPSD46842.2020.9170081.
[17] L. Zhang, J. Wei*, Z. Zheng, W. Song, S. Yang, S. Feng, and K. J. Chen*, “700-V p-GaN gate HEMT with low-voltage third quadrant operation using area-efficient built-in diode,” in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 521-524, doi: 10.1109/ISPSD46842.2020.9170075.
[18] (Invited) K. J. Chen, J. Wei, G. Tang, H. Xu, Z. Zheng, L. Zhang, and W. Song, “Planar GaN power integration – The world is flat,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2020, pp. 573-576, doi: 10.1109/IEDM13553.2020.9372069.
[19] J. He, J. Wei, Z. Zheng, S. Yang, Y. Li, B. Huang, and K. J. Chen, “Low-temperature accelerated gate reliability of Schottky-type p-GaN gate HEMTs”, in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 290-293, doi: 10.1109/ISPSD46842.2020.9170191.
[20] J. Sun, J. Wei, Z. Zheng, G. Lyu, K. J. Chen, “Distinct short circuit capability of 650V p-GaN gate HEMTs under single and repetitive tests”, in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 313-316, doi: 10.1109/ISPSD46842.2020.9170148.
[21] M. Hua, J. Chen, C. Wang, L. Liu, L. Li, J. Zhao, Z. Jiang, J. Wei, L. Zhang, Z. Zheng, and K. J. Chen, “E-mode p-GaN gate HEMT with p-FET bridge for higher VTH and enhanced VTH stability,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2020, pp. 473-476, doi: 10.1109/IEDM13553.2020.9371969.
[22] J. Chen, M. Hua, J. He, J. Wei, and K. J. Chen, “Impact of hole-deficiency and charge trapping on threshold voltage stability of p-GaN HEMT under reverse-bias stress,” in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 18-21, doi: 10.1109/ISPSD46842.2020.9170043.
[23] G. Lyu, Y. Wang, J. Wei, Z. Zheng, J. Sun, M. Hua, L. Zhang, and K. J. Chen, “Dv/Dt-control of 1200-V co-packaged SiCJFET/GaN-HEMT cascode device,” in Proc. ISPSD, Vienna, Austria, Sep. 2020, pp. 86-89, doi: 10.1109/ISPSD46842.2020.9170127.
[24] Y. Wang, G. Lyu, J. Wei, Z. Zheng, K. Zhong, and K. J. Chen, “All-WBG cascode device with p-GaN gate HEMT and SiC JFET for high-frequency and high-temperature power switching applications,” in Proc. WiPDA Asia, Suita, Japan, Sep. 2020, pp. 1-5, doi: 10.1109/WiPDAAsia49671.2020.9360291.
Year 2019
[25] (Invited) J. Wei and K. J. Chen, “Development of GaN power integrated circuits,” in Extended Abstracts of the International Conference on Solid State Devices and Materials, Nagoya, Japan, Sep. 2019, pp. 441-442.
[26] J. Wei, H. Xu, R. Xie, M. Zhang, H. Wang, Y. Wang, K. Zhong, M. Hua, J. He, and K. J. Chen, “Dynamic threshold voltage in p-GaN gate HEMT,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 291-294, doi: 10.1109/ISPSD.2019.8757602.
[27] J. Wei, M. Zhang, H. Jiang, B. Li, Z. Zheng, and K. J. Chen, “Investigations of p-shielded SiC trench IGBT with considerations on IE effect, oxide protection and dynamic degradation,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 199-202, doi: 10.1109/ISPSD.2019.8757642.
[28] J. Lei, J. Wei, G. Tang, Z. Zhang, Q. Qian, M. Hua, Z. Zheng, Y. Wang, and K. J. Chen, “Charge-modulated Schottky barrier lowering effect in GaN double-channel lateral power SBDs with a gated anode,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 459-462, doi: 10.1109/ISPSD.2019.8757606.
[29] J. Sun, J. Wei and K. J. Chen, “Repetitive short circuit energy dependent VTH instability of 1.2kV SiC power MOSFETs,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 263-266, doi: 10.1109/ISPSD.2019.8757639.
[30] J. He, J. Wei, S. Yang, and K. J. Chen, “Temperature-dependent gate degradation of p-GaN gate HEMTs under static and dynamic positive gate stress,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 295-298, doi: 10.1109/ISPSD.2019.8757574.
[31] Y. Wang, J. Wei, S. Yang, J. Lei, M. Hua, and K. J. Chen, “Characterization of dynamic IOFF in Schottky-type p-GaN gate HEMTs,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 463-466, doi: 10.1109/ISPSD.2019.8757660.
[32] S. Yang, S. Huang, J. Wei, Y. Wang, Z. Zheng, J. He, and K. J. Chen, “DLTS investigation of transient capacitance and trap states on p-GaN gate HEMT structures,” in Proc. ICNS, Bellevue, Washington, USA, Jul. 2019, pp. JP01.04.
[33] W. Song, Z. Zheng, J. Lei, J. Wei, L. Yuan, and K. J. Chen, “Double-channel high-electron-mobility transistor for linearity enhancement in RF/microwave applications,” in Proc. Compound Semiconductor Week, Nara, Japan, May 2019, p. TuP-C-6, doi: 10.1109/ICIPRM.2019.8819146.
[34] Z. Zheng, M. Hua, J. Wei, Z. Zhang, and K. J. Chen, “Identifying the location of hole-induced gate degradation in LPCVD-SiNx/GaN MIS-FETs under high reverse-bias stress,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 435-438, doi: 10.1109/ISPSD.2019.8757652.
[35] H. Xu, G. Tang, J. Wei, and K. J. Chen, “Integrated high-speed over-current protection circuit for GaN power transistors,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 275-278, doi: 10.1109/ISPSD.2019.8757685.
[36] M. Hua, S. Yang, Z. Zheng, J. Wei, Z. Zhang, and K. J. Chen, “Effects of substrate termination on reverse-bias stress stability of normally-off lateral GaN-on-Si MIS-FETs,” in Proc. ISPSD, Shanghai, China, May 2019, pp. 467-470, doi: 10.1109/ISPSD.2019.8757600.
[37] M. Hua, S. Yang, J. Wei, Z. Zheng, J. He, and K. J. Chen, “Reverse-bias stability and reliability of enhancement-mode GaN based MIS-FET,” in Proc. ASICON, Chongqing, China, Oct. 2019, pp. 1-4, doi: 10.1109/ASICON47005.2019.8983535.
Year 2018
[38] J. Wei, M. Zhang, H. Jiang, S. To, S. Kim, J. Kim, and K. J. Chen, “SiC trench IGBT with diode-clamped p-shield for oxide protection and enhanced conductivity modulation,” in Proc. ISPSD, Chicago, IL, USA, May 2018, pp. 411-414, doi: 10.1109/ISPSD.2018.8393690.
[39] J. Lei, J. Wei, G. Tang, and K. J. Chen, “Reverse-blocking AlGaN/GaN normally-off MIS-HEMT with double-recessed gated Schottky drain,” in Proc. ISPSD, Chicago, IL, USA, May 2018, pp. 276-279, doi: 10.1109/ISPSD.2018.8393656.
[40] R. Xie, G. Xu, X. Yang, G. Tang, J. Wei, Y. Tian, F. Zhang, W. Chen, L. Wang, and K. J. Chen, “Modeling the gate driver IC for GaN transistor: a black-box approach,” in Proc. APEC, San Antonio, TX, USA, Mar. 2018, pp. 2900-2904, doi: 10.1109/APEC.2018.8341429.
[41] M. Hua, X. Cai, S. Yang, Z. Zhang, Z. Zheng, J. Wei, J. He, and K. J. Chen, “Suppressed hole-induced degradation in E-mode GaN MIS-FETs with crystalline GaOxN1-x channel,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2018, pp. 695-698, doi: 10.1109/IEDM.2018.8614687.
Year 2017
[42] J. Wei, M. Zhang, H. Jiang, H. Wang, and K. J. Chen, “Charge storage effect in SiC Trench MOSFET with a floating p-shield and its impact on dynamic performances,” in Proc. ISPSD, Sapporo, Japan, May 2017, pp. 387-390, doi: 10.23919/ISPSD.2017.7988985.
[43] J. Wei, Y. Wang, M. Zhang, H. Jiang, and K. J. Chen, “High-speed power MOSFET with low reverse transfer capacitance using a trench/planar gate architecture,” in Proc. ISPSD, Sapporo, Japan, May 2017, pp. 331-334, doi: 10.23919/ISPSD.2017.7988956.
[44] M. Hua, J. Wei, Q. Bao, Z. Zhang, J. He, Z. Zheng, J. Lei, and K. J. Chen, “Reverse-bias stability and reliability of hole-barrier-free E-mode LPCVD-SiNx/GaN MIS-FETs,” in IEDM Tech. Dig., San Francisco, USA, Dec. 2017, pp. 741-744, doi: 10.1109/IEDM.2017.8268489.
[45] J. Lei, J. Wei, G. Tang, Q. Qian, M. Hua, Z. Zhang, Z. Zheng, and K. J. Chen, “An interdigitated GaN MIS-HEMT/SBD normally-off power switching device with low ON-resistance and low reverse conduction loss,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2017, pp. 609-612, doi: 10.1109/IEDM.2017.8268456.
[46] H. Jiang, J. Wei, X. Dai, C. Zheng, M. Ke, X. Deng, Y. Sharma, I. Deviny, and P. Mawby, “SiC MOSFET with built-in SBD for reduction of reverse recovery charge and switching loss in 10-kV applications,” in Proc. ISPSD, Sapporo, Japan, May 2017, pp. 49-52, doi: 10.23919/ISPSD.2017.7988890.
[47] G. Tang, J. Wei, Z. Zhang, X. Tang, M. Hua, H. Wang, and K. J. Chen, “Impact of substrate termination on dynamic performance of GaN-on-Si lateral power devices,” in Proc. ISPSD, Sapporo, Japan, May 2017, pp. 235-238, doi: 10.23919/ISPSD.2017.7988920.
[48] G. Tang, J. Wei, Z. Zhang, X. Tang, M. Hua, H. Wang, and K. J. Chen, “Characterization and analysis of dynamic RON of GaN-on-Si lateral power devices with grounded and floating Si substrate,” in Proc. ICNS, Strasbourg, France, Jul. 2017, p. C3.3.
[49] M. Hua, Q. Qian, J. Wei, Z. Zhang, G. Tang, and K. J. Chen, “TDDB and PBTI characterizations of fully-recessed E-mode GaN MIS-FETs with LPCVD-SiNx/PECVD-SiNx gate dielectric stack,” in Proc. CS ManTech, Indian Wells, CA, USA, May 2017, pp. 18.4.
[50] M. Hua, Q. Qian, J. Wei, Z. Zhang, G. Tang, and K. J. Chen, “PBTI and NBTI of fully-recessed E-mode LPCVD-SiNx/GaN MIS-FETs with PECVD-SiNx interfacial protection layer,” in Proc. ICNS, Strasbourg, France, Jul. 2017, pp. C7.4.
[51] M. Hua, Z. Zhang, Q. Qian, J. Wei, Q. Bao, G. Tang, and K. J. Chen, “High-performance fully-recessed enhancement-mode GaN MIS-FETs with crystalline oxide interlayer,” in Proc. ISPSD, Sapporo, Japan, May 2017, pp. 89-92, doi: 10.23919/ISPSD.2017.7988900.
Year 2016
[52] J. Wei, H. Jiang, Q. Jiang, and K. J. Chen, “Proposal of a novel GaN/SiC hybrid FET (HyFET) with enhanced performance for high-voltage switching applications,” in Proc. ISPSD, Prague, Czech Republic, Jun. 2016, pp. 99-102, doi: 10.1109/ISPSD.2016.7520787.
[53] J. Wei, S. Liu, B. Li, X. Tang, G. Tang, Z. Zhang, and K. J. Chen, “Critical heterostructure design for low on-resistance normally-off double-channel MOS-HEMT,” in Proc. ISCS, Toyama, Japan, Jun. 2016, p. 1TuB1-6, doi: 10.1109/ICIPRM.2016.7528768.
[54] H. Jiang, J. Wei, X. Dai, M. Ke, C. Zheng, and I. Deviny, “Silicon carbide split-gate MOSFET with merged Schottky barrier diode and reduced switching loss,” in Proc. ISPSD, Prague, Czech Republic, Jun. 2016, pp. 59-62, doi: 10.1109/ISPSD.2016.7520777.
[55] M. Hua, Z. Zhang, J. Wei, J. Lei, G. Tang, K. Fu, Y. Cai, B. Zhang, and K. J. Chen, “Integration of LPCVD-SiNx gate dielectric with recessed-gate E-mode GaN MIS-FETs: toward high performance, high stability and long TDDB lifetime,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2016, pp. 260-263, doi: 10.1109/IEDM.2016.7838388.
[56] H. Wang, R. Xie, C. Liu, J. Wei, G. Tang, and K. J. Chen, “Maximizing the performance of 650 V p-GaN gate HEMTs: dynamic RON characterization and gate-drive design considerations,” in Proc. ECCE, Wilwaukee, WI, USA, Sep. 2016, pp. 1-6, doi: 10.1109/ECCE.2016.7855231.
[57] X. Tang, B. Li, H. Wang, J. Wei, G. Tang, Z. Zhang, and K. J. Chen, “Impact of integrated photonic-Ohmic drain on static and dynamic characteristics of GaN-on-Si heterojunction power transistors,” in Proc. ISPSD, Prague, Czech Republic, Jun. 2016, pp. 31-34, doi: 10.1109/ISPSD.2016.7520770.
Year 2015
[58] J. Wei, S. Liu, B. Li, X. Tang, Y. Lu, C. Liu, M. Hua, Z. Zhang, G. Tang, and K. J. Chen, “Enhancement-mode GaN double-channel MOS-HEMT with low on-resistance and robust gate recess,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2015, pp. 225-228, doi: 10.1109/IEDM.2015.7409662.
[59] X. Tang, B. Li, Y. Lu, H. Wang, C. Liu, J. Wei, and K. J. Chen, “III-nitride transistors with photonic-ohmic drain for enhanced dynamic performances,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2015, pp. 907-910, doi: 10.1109/IEDM.2015.7409832.
Year 2012
[60] M. Zhang, J. Wei, Z. Li, W. Chen, M. Ren, and J. Zhang, “A novel rectifier with low turn-on voltage utilizing three conducting mechanisms at different voltage levels,” in Proc. ICSICT, Xi'an, China, Oct. 2012, pp. 1154-1156, doi: 10.1109/ICSICT.2012.6467748.