An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique Liu#, Ying, Yufei Ma#*, ..., Jiayoon Ru, Ru HUANG, and Le Ye*. “An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2023). Links
A 22-nm Delta-Sigma Computing-In-Memory (ΔΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing Chen#, Peiyu, Meng Wu#, ..., Yufei Ma*, Le Ye*, and Ru HUANG. “A 22-nm Delta-Sigma Computing-In-Memory (ΔΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.” IEEE International Solid-State Circuits Conference (ISSCC 2023), 2023. Links
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network Liu, Ying, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang*, Ru HUANG, Le Ye, and Yufei Ma*. “Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network.” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2024). Links
