科研成果 by Type: Conference Paper

This paper studies the high priests found in inscriptions from Amastris concerning the Koinon of the Cities in Pontus (henceforth “the Koinon”), commonly recognized as an assembly of cities in coastal Paphlagonia (Marek 2003, Vitale 2012; contra Loriot 2006).  The Amastrian high priests (7 in total) comprise of three types: 1) ἀρχιερεὺς τοῦ Πόντοῦ, which can be securely associated with the Koinon; 2) ἀρχιερεύς, without specific designation as to what sort of imperial or local cult it was in charge; 3) ὁ τοῦ ἐπουρανίου Θεοῦ Σεβαστοῦ ἀρχ[ιερεὺς διὰ βίου, which also has the Latin equivalent Divi Aug. perpetuus sacerdos inscribed together as a bilingual text.  Should all three types titles be interpreted as the same office? Christian Marek (2003) assumed that they were: he included 2) and 3) under 1), without clarification. Xavier Loriot (2006) assumed differently: in his tabulation of dignitaries of Pontus, he omitted the office holders of 2) and 3), and he also did not state his rationale.  The discrepancy is significant because of dating. Time-reckoning markers on inscriptions of 2) and 3) help date the former to 62 CE, and the latter c. 50 CE, all considerably earlier than the earliest inscription in 1), which is Trajanic. The problem, on the other hand, is that Marek’s inclusion of 2) and 3) may be wrong: Frija (2012) demonstrated that when a high priesthood was not specified, they could be instead high priests of the municipal imperial cult.  This paper considers the possibility that 2) and 3) may have been local/municipal office(s), and could have been the precursor to the High Priesthood of Pontus. Particular emphasis will be on the bilingual text of 3), which contain the surprising attribution ἐπουρανίος, commonly associated with Zeus or Theos Hypsistos and without a Latin equivalent.

© 2017 IEEE. Routing is a time-consuming process in the FPGA design flow. Parallelization is a promising direction to accelerate the routing. While synchronous parallelization can converge a feasible solution, the ideal speedup is rarely achieved due to excessive communication overheads. Asynchronous parallelization can provide an almost linear speedup, but it is difficult to converge in the limited number of iterations due to net dependency. In this paper we propose SAPRoute, which coordinates synchronous and asynchronous parallelism on distributed multiprocessing environment to accelerate the routing for FPGAs. The objective is to boost the more speedup of parallel routing algorithm under the requirement of convergence. To the best of our knowledge, this is the first work to study the impact of synchronization and asynchronization during parallelization. Experimental results show that our approach have negligible explicit synchronization overhead and achieves significant speedup improvement over a set of commonly used benchmarks. Notably, SAPRoute produces the speedup of 24.27 x on average compared to the default serial solution.

© 2017 IEEE. Quantitative effects of Moore's Law have driven qualitative changes in FPGA architecture, applications, and tools. As a consequence, the existing EDA tools takes several hours or even days to implement the applications onto FPGAs. Typically, routing is a very time-consuming process in the EDA design flow. While several attempts have accelerated this process through parallelization, they still do not provide a strong parallel scheme for FPGA routing. In this paper we introduce a dependency-aware parallel approach, named Bamboo, to accelerate the routing time for FPGAs. With the dependency detection, Bamboo partitions the nets into multiple subsets, where the nets in the same subsets are independent, and the dependency only exists among different subsets. Specifically, the independent nets in the same subset are routed in parallel, and the subsets are processed in serial according to the original routing ordering. The partitioning problem is solved optimally using dynamic programming, and the parallelization is implemented by speculative parallelism on a single GPU. Experimental results show that our approach achieves an average of 15.13x speedup with negligible influence on the routing quality. Most importantly, it effectively maintains deterministic results and always produces the same results as the serial version.

The past five years have witnessed the significant breakthrough of perovskite solar cells (PSCs). High certificated power conversion efficiency (PCE) of 22.1% was achieved in a short time after the inorganic-organic perovskite was firstly used as the light absorber in the solar cells. It is believed that PSCs now become one of the most promising photovoltaic in the new-generation solar cells, which may rival silicon based solar cells. In this article, simplified planar perovskite solar cells without a hole-blocking layer were fabricated by a two-step spin-coating method, and the highest PCE of 15.1% was achieved with an average PCE of 13.6%. Moreover, it is found that the hysteresis effect is reduced in this kind of devices. The research on improved performance for the PSCs with simplified device architecture is very important both for understanding the working mechanism of cells, and for fabricating low-cost and high-performance PSCs to approach commercial applications. (C) 2017 Published by Elsevier Ltd.

This work reports a kilovolt and low current collapse normally-off GaN MOSHEMT on silicon substrate. The device with a drift length of 3 mum features a threshold voltage of 1.7 V and an output current of 430 mA/mm at 8 V gate bias. The off-state breakdown voltage (BV) is as high as 1021 V (800 V) defined at a drain leakage criterion of 10 muA/mm with floating (grounded) substrate. The corresponding breakdown electric field is 3.4 MV/cm and the Baliga's figure-of-merit (BFOM) is 1.6 GW/cm2. A small degradation of the dynamic on-resistance (Ron, d) about 30% is observed with a short pulse width of 500 ns and a quiescent drain bias of 60 V. The record value is supposed to benefit from the intrinsic step-graded field plate, high quality LPCVD Si3N4 passivation and material optimization of 4.5 mum thick epitaxial layer.