科研成果 by Type: Conference Paper

2018
刘宇初. 从博物馆文创实践看我国图书馆文创产品开发的问题及策略, in 中国图书馆学会年会(2017年). 北京: 国家图书馆出版社; 2018:335-340.
樊振强, 吴志鹏, 谢依钒, 刘奕, 陈永强. 基于情景计算的城市地震灾害分析, in 第17届北方七省市区力学学会学术会议. 焦作; 2018.
陈永强, 刘奕. 情景计算及其在公共安全中的应用, in 2018公共安全高峰论坛. 崇礼; 2018:144.
林官明. 沙纹形成的表面波似然机制, in 首届中国空气动力学大会.Vol I. 中国绵阳 ; 2018:95-97.
从超男, 陈永强. 石墨烯/蒙脱土/聚合物复合材料的细观力学模型, in 全国固体力学学术会议.; 2018.
黄君豪, 陈永强. 边界元法单元积分精度的几何指标研究, in 北方七省市区力学会议. 河南省力学学会; 2018.
吴志鹏, 陈永强. 高性能边界元法模拟复合材料黏性界面分离, in 北方七省市区力学会议.; 2018.
2017
Jia T, Gu J. A 0.3-0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications, in VLSI Symposium on Circuits (VLSI).; 2017.
Shen L, Lu N, Sun N. A 1V 0.25uW inverter-stacking amplifier with 1.07 noise efficiency factor, in 2017 Symposium on VLSI Circuits.; 2017:C140-C141.Abstract
This paper presents a highly power efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves 6-time current reuse, thereby significantly boosting gm and lowering noise but without increasing power. A novel biasing scheme is devised to ensure robust operation under 1V supply. A prototype in 180nm CMOS has 5.5uV rms noise within 10kHz BW while consuming only 0.25uW, leading to a noise efficiency factor (NEF) of 1.07, which is the best among reported amplifiers.
Ao Y, Yang C, Wang X, Xue W, Fu H, Liu F, Gan L, Xu P, Ma W. 26 PFLOPS Stencil Computations for Atmospheric Modeling on Sunway TaihuLight, in Proc. 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS'17). IEEE; 2017:535–544. 访问链接
Gong J, Yang T, Zhou Y, Yang D, Chen S, Cui B, Li X. Abc: a practicable sketch framework for non-uniform multisets, in IEEE BigData.; 2017:2380–2389.
Wang Z, Zhang P. Activity Patterns of Collaborative Sensemaking in Small Discussion Groups, in iConference '17. Wuhan, China; 2017. 访问链接
Wu C-Y. Amastrian High Priests: Leading Men of the Koinon of the Cities in Pontus?, in Annual Meeting of Postgraduates in Ancient History (AMPAH). King’s College London, Strand campus, London; 2017.Abstract
This paper studies the high priests found in inscriptions from Amastris concerning the Koinon of the Cities in Pontus (henceforth “the Koinon”), commonly recognized as an assembly of cities in coastal Paphlagonia (Marek 2003, Vitale 2012; contra Loriot 2006).  The Amastrian high priests (7 in total) comprise of three types: 1) ἀρχιερεὺς τοῦ Πόντοῦ, which can be securely associated with the Koinon; 2) ἀρχιερεύς, without specific designation as to what sort of imperial or local cult it was in charge; 3) ὁ τοῦ ἐπουρανίου Θεοῦ Σεβαστοῦ ἀρχ[ιερεὺς διὰ βίου, which also has the Latin equivalent Divi Aug. perpetuus sacerdos inscribed together as a bilingual text.  Should all three types titles be interpreted as the same office? Christian Marek (2003) assumed that they were: he included 2) and 3) under 1), without clarification. Xavier Loriot (2006) assumed differently: in his tabulation of dignitaries of Pontus, he omitted the office holders of 2) and 3), and he also did not state his rationale.  The discrepancy is significant because of dating. Time-reckoning markers on inscriptions of 2) and 3) help date the former to 62 CE, and the latter c. 50 CE, all considerably earlier than the earliest inscription in 1), which is Trajanic. The problem, on the other hand, is that Marek’s inclusion of 2) and 3) may be wrong: Frija (2012) demonstrated that when a high priesthood was not specified, they could be instead high priests of the municipal imperial cult.  This paper considers the possibility that 2) and 3) may have been local/municipal office(s), and could have been the precursor to the High Priesthood of Pontus. Particular emphasis will be on the bilingual text of 3), which contain the surprising attribution ἐπουρανίος, commonly associated with Zeus or Theos Hypsistos and without a Latin equivalent.
XIAO L. The Application of Knowledge Management in Organizational Restructuring of Academic Libraries: A Case Study of Peking University Library. IFLA open session, in IFLA World Library and Information Congress 2017 (83rd IFLA General Conference and Assembly). Wrocław, Poland : IFLA Library; 2017. 访问链接
Zhang J, Wang Y, Zhang X, HUANG R. Compact Digital-Controlled Neuromorphic circuit with Low Power Consumption, in IEEE International Symposium on Circuits and Systems (ISCAS). Baltimore, USA; 2017:2062-2065.
Shen M, Luo G, Xiao N. A coordinated synchronous and asynchronous parallel routing approach for FPGAs, in 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).Vol 2017-Novem. IEEE; 2017:577–584. 访问链接Abstract
© 2017 IEEE. Routing is a time-consuming process in the FPGA design flow. Parallelization is a promising direction to accelerate the routing. While synchronous parallelization can converge a feasible solution, the ideal speedup is rarely achieved due to excessive communication overheads. Asynchronous parallelization can provide an almost linear speedup, but it is difficult to converge in the limited number of iterations due to net dependency. In this paper we propose SAPRoute, which coordinates synchronous and asynchronous parallelism on distributed multiprocessing environment to accelerate the routing for FPGAs. The objective is to boost the more speedup of parallel routing algorithm under the requirement of convergence. To the best of our knowledge, this is the first work to study the impact of synchronization and asynchronization during parallelization. Experimental results show that our approach have negligible explicit synchronization overhead and achieves significant speedup improvement over a set of commonly used benchmarks. Notably, SAPRoute produces the speedup of 24.27 x on average compared to the default serial solution.
Shen M, Luo G. Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion, in Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '17. New York, New York, USA: ACM Press; 2017:105–114. 访问链接
Zhang R, Li W, Tan W, Mo T. Deep and Shallow Model for Insurance Churn Prediction Service, in Services Computing (SCC), 2017 IEEE International Conference on. IEEE; 2017:346–353.
Shen M, Xiao N, Luo G. Dependency-Aware Parallel Routing for Large-Scale FPGAs, in 2017 IEEE International Conference on Computer Design (ICCD). IEEE; 2017:249–256. 访问链接Abstract
© 2017 IEEE. Quantitative effects of Moore's Law have driven qualitative changes in FPGA architecture, applications, and tools. As a consequence, the existing EDA tools takes several hours or even days to implement the applications onto FPGAs. Typically, routing is a very time-consuming process in the EDA design flow. While several attempts have accelerated this process through parallelization, they still do not provide a strong parallel scheme for FPGA routing. In this paper we introduce a dependency-aware parallel approach, named Bamboo, to accelerate the routing time for FPGAs. With the dependency detection, Bamboo partitions the nets into multiple subsets, where the nets in the same subsets are independent, and the dependency only exists among different subsets. Specifically, the independent nets in the same subset are routed in parallel, and the subsets are processed in serial according to the original routing ordering. The partitioning problem is solved optimally using dynamic programming, and the parallelization is implemented by speculative parallelism on a single GPU. Experimental results show that our approach achieves an average of 15.13x speedup with negligible influence on the routing quality. Most importantly, it effectively maintains deterministic results and always produces the same results as the serial version.
Yang D, Tian D, Gong J, Gao S, Yang T, Li X. Difference bloom filter: A probabilistic structure for multi-set membership query, in IEEE ICC.; 2017.

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