This paper presents a hybrid 4th-order delta-sigma modulator (DSM). It combines a continuous-time (CT) loop filter and a discrete-time (DT) passive 2nd-order noise-shaping SAR (NSSAR). Since the 2nd-order NS-SAR is robust against PVT variation, the stability of this 4th-order DSM is similar to that of a 2nd-order CT-DSM. The CT loop filter is based on single-amplifier bi-quad (SAB) structure. As a result, only one OTA is used to achieve 4th-order noise shaping, leading to a high power efficiency. Moreover, this work implements both excess loop delay (ELD) compensation and an input feedforward path inside the NS-SAR in the charge domain, further reducing the circuit complexity and the OTA power. Overall, this work achieves 81 dB SNDR over 12.5 MHz with 3.7 mW power, leading to a Schreier FoM of 176 dB.
This letter presents a 3T eDRAM in-memory physically unclonable function (PUF) for low-cost Internet of Things (IoT) applications. The proposed design integrates PUF to eDRAM with a small
peripheral overhead. With the subthreshold leakage of the bit-cell read path exploited as the entropy source, two adjacent 3T eDRAMs (with 2 × 197 F2 = 394 F2 area) race to generate the key bit. To overcome voltage and temperature variations, the spatial majority voting (SMV) is adopted. Implemented in 65-nm CMOS, the proposed eDRAM PUF achieves <0.35% bit error rate (BER) across a voltage range of 1.0–1.2 V and temperature range of 0 ◦C–60 ◦C, presenting a low-cost and robust solution for IoT security.
For neural network (NN) applications at the edge ofAI, computing-in-memory (CIM) demonstrates promising energyefficiency. However, when the network size grows while fulfillingthe accuracy requirements of increasingly complicated applicationscenarios, significant memory consumption becomes an issue.Model pruning is a typical compression approach for solvingthis problem, but it does not fully exploit the energy efficiencyadvantage of conventional CIMs, because of the dynamic distributionof sparse weights and the increased data movement energyconsumption of reading sparsity indexes from outside the chip.Therefore, we propose a vector-wise dynamic-sparsity controllingand computing in-memory structure (DS-CIM) that accomplishesboth sparsity control and computation of weights in SRAM, toimprove the energy efficiency of the vector-wise sparse pruningmodel. Implemented in a 65 nm CMOS process, the measurementresults show that the proposed DS-CIM macro can save upto 50.4% of computational energy consumption, while ensuringthe accuracy of vector-wise pruning models. The test chip canalso achieve 87.88% accuracy on the CIFAR-10 dataset at 4-bitprecision in inputs and weights, and it achieves 530.2TOPS/W(normalized to 1 bit) energy efficiency.
High-precision large dynamic-range (DR) current-sensing front-ends are widely used in biomedical applications, such as patch-clamp, molecular concentration detection, and gene sequencing. The new gene sequencers require low-noise analog front-ends capable of sensing large DR current (>100 dB) down to sub-pA-level. At this level of precision, oversampled data converters are usually used. However, given the limited oversampling ratio in high throughput applications, it is very challenging to achieve a sub-pA-level sensitivity and >100dB DR within the limited area and energy budgets [1]. In [2], a 140dB DR is achieved using a multi-bit delta-sigma modulator (DSM), but the power consumption is over 1mW and the current sensitivity is limited to 6.3pA. An hourglass ADC achieving a 100fA sensitivity and 140dB DR is presented in [3], but is limited by conversion rate and relatively high power consumption (295μW). For a 100Hz bandwidth, its noise floor increases to 18pA.