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简介

主要研究方向

后摩尔时代超低功耗微纳电子器件及其在逻辑、存储与新型计算等领域的应用。

学习工作经历

  • 2024.02 - 今，长聘副教授、研究员、博士生导师，北京大学
  • 2017.09 - 2024.01，助理教授、研究员、博士生导师，北京大学
  • 2015.10 - 2017.09，博士后，北京大学
  • 2010.09 - 2015.07，博士，北京大学
  • 2006.09 - 2010.07，学士，北京大学

部分学术兼职

  • IEEE International Electron Devices Meeting (IEDM) Technical Program Committee
  • IEEE Electron Devices Society VLSI Technology & Circuits Technical Committee
  • IEEE Electron Devices Society Women in Engineering Committee
  • 中国电子学会青年女科学家俱乐部第一届理事会理事

研究成果概况

主要包括：（1）研制出的新机理超低功耗器件打破了国际上硅基隧穿器件的亚阈摆幅纪录，器件综合性能为国际报道中同类器件最高，相关成果被国际半导体技术路线指南（ITRS）及国际器件与系统路线指南（IRDS）引用，并与国内领先的集成电路制造企业和创新平台等合作研制了世界上首个基于12英寸CMOS大生产线的超低功耗互补隧穿器件集成技术及电路芯片；（2）国际上首次在单独铁电电容中直接观测到负微分电容现象，针对低功耗负电容晶体管中最具争议的稳态负电容机制问题，提出并验证了符合物理本质的动态极化翻转负电容理论；（3）国际上首次利用铁电极化翻转模拟生物神经元动态行为提出并实验实现了基于新型超低功耗仿生铁电晶体管的脉冲神经元，极大降低了脉冲神经元的硬件开销和能耗，为大规模、高集成的超低功耗神经形态计算芯片奠定了重要器件基础。已发表论文100余篇，其中以第一作者/通讯作者身份在微电子领域顶级国际会议IEDM与VLSI上发表论文15篇（含一作6篇）。已获国际授权专利10余项、国内授权专利50余项，部分成果转移到中芯国际。2023年获中国青年女科学家奖，2020年获科学探索奖、求是杰出青年学者奖，2019年获IEEE Electron Devices Society Early Career Award，2018年获国家优秀青年科学基金项目资助。

部分邀请报告

  • 2023年5月，中国电子学会青年科学家论坛之第四届半导体青年学术会议，上海，上海虹桥绿地铂瑞酒店，特邀报告
  • 2022年12月，北京微电子国际研讨会暨IC WORLD大会存储器技术及应用发展研讨论坛，北京，北京朝林松源酒店，特邀报告
  • Oct. 2022, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), online. (Invited)
  • Sep. 2022, IEEE International Conference on IC Design and Technology (ICICDT), online. (Invited)
  • Aug. 2022, IEEE International Flexible Electronics Technology Conference (IFETC), Qingdao, China. (Invited)
  • Mar. 2022, IEEE Electron Devices Technology & Manufacturing Conference (EDTM), online. (Invited)
  • 2021年10月，Symposium on Low-Dimensional Material Application and Standardization (LDMAS)（第四届低维材料应用与标准研讨会），北京，西郊宾馆，特邀报告
  • 2021年7月，第二十三届全国半导体物理学术会议，西安，西安曲江国际会议中心，特邀报告
  • Apr. 2021, Virtual MRS Spring Meeting, online. (Invited)
  • Nov. 2020, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), online. (Invited)
  • Oct. 2020, IEEE Nanotechnology Materials and Devices Conference (NMDC), online. (Invited)
  • Oct. 2019, IEEE Non-Volatile Memory Technology Symposium (NVMTS), Durham, USA. (Invited)
  • Apr. 2019, MRS Spring Meeting, Phoenix, USA. (Invited)
  • Mar. 2019, China Semiconductor Technology International Conference (CSTIC), Shanghai, China. (Invited)
  • 2019年1月，中国科学院学部科学与技术前沿论坛——新时期半导体科学技术战略发展论坛，北京，中国科学院学术会堂，主题报告
  • 2018年12月，Future Chips Forum: Reconfigurable Computing in a New Golden Age （未来芯片论坛：可重构计算的黄金时代），北京，清华大学，特邀报告
  • 2018年11月，中国电子学会第二十四届青年学术年会，北京，中央民族大学，特邀报告
  • 2018年10月，中国电子学会电子信息青年科学家论坛暨第二届半导体青年学术会议，郑州，郑州大学，特邀报告

部分发表论文

  • Yaoru Hou#, Kaifeng Wang#, Chenxing Liu-Sun, Jianfeng Hang, Xinfang Tong, Chunyu Peng, Yongqin Wu, Ye Ren, Weihai Bu, Xin Si, Bo Liu, Xiulong Wu, Jun Yang, Hao Cai*, Qianqian Huang*, Ru Huang, “A Sub-100nA Ultra-low Leakage MCU Embedding Always-on Domain Hybrid Tunnel FET-CMOS on 300mm Foundry Platform”, in IEDM Tech. Dig., 2023.
  • Zhiyuan Fu#, Shengjie Cao#, Hao Zheng, Jin Luo, Qianqian Huang* and Ru Huang*, “First Demonstration of Hafnia-based Selector-Free FeRAM with High Disturb Immunity through Design Technology Co-Optimization”, in IEDM Tech. Dig., 2023.
  • Chang Su, Ning Feng, Kaifeng Wang, Lining Zhang, Ru Huang* and Qianqian Huang*, “A Physical MFIS-FeFET Model with Awareness of Drain-Induced Spatially-Distributed Polarization and Ferroelectric Parametric Fluctuation”, in SISPAD, 2023.
  • Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang, Fangxing Zhang, Lining Zhang, Chunyu Peng, Xiulong Wu, Le Ye, Kai Zheng, Jin Kang, Xusheng Wu, Weihai Bu*, Ru Huang* and Qianqian Huang*, “First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology”, in ESSDERC, 2023, pp.13-16.
  • Chang Su, Zhongxin Liang, Zhiyuan Fu, Shaodi Xu, Kaifeng Wang, Puyang Cai, Liang Chen, Ru Huang* and Qianqian Huang*, “New Insights into Read Current Margin and Memory Window of HfO2-based Ferroelectric FET with Re-exploration of the Role of Ferroelectric Dynamics and Interface Charges during Readout”, in ESSDERC, 2023, pp. 89-92.
  • Jin Luo, Tianyi Liu, Zhiyuan Fu, Xinming Wei, Qianqian Huang*, and Ru Huang*, “Ferroelectric FET based Signed Synapses of Excitatory and Inhibitory Connection for Stochastic Spiking Neural Network based Optimizer”, in IEEE EDTM, 2023, pp. 307-309. (Best Student Paper Award)
  • Zhiyuan Fu, Kaifeng Wang, Boyi Fu, Shaodi Xu, Hao Zheng, Jin Luo, Chang Su, Weikai Xu, Xiao Lv, Qianqian Huang* and Ru Huang*, “Novel Energy-efficient Hafnia-based Ferroelectric Processing-in-Sensor with in-situ Motion Detection and Four-quarter Multiplication”, in IEDM Tech. Dig., 2022.
  • Jin Luo, Hanyong Shao, Boyi Fu, Zhiyuan Fu, Weikai Xu, Kaifeng Wang, Mengxuan Yang, Yiqing Li, Xiao Lv, Qianqian Huang* and Ru Huang*, “Novel Ferroelectric Tunnel FinFET based Encryption-embedded Computing-in-Memory for Secure AI with High Area- and Energy-Efficiency”, in IEDM Tech. Dig., 2022.
  • Kaifeng Wang, Qianqian Huang*, Yongqin Wu, Ye Ren, Renjie Wei, Zhixuan Wang, Libo Yang, Fangxing Zhang, Kexing Geng, Yiqing Li, Mengxuan Yang, Jin Luo, Ying Liu, Kai Zheng, Jin Kang, Le Ye, Lining Zhang, Weihai Bu* and Ru Huang*, “A Novel Energy-Efficient Salicide-Enhanced Tunnel Device Technology Based on 300 mm Foundry Platform Towards AIoT Applications”, in ESSDERC, 2022, pp. 360-363.
  • Chang Su, Weikai Xu, Qianqian Huang*, Lining Zhang and Ru Huang*, “New Insights into the Effect of Spatially Distributed Polarization in Ferroelectric FET on Content Addressable Memory Operation for Machine Learning Applications”, in SISPAD, 2022, pp. 9-10.
  • Chang Su, Qianqian Huang*, Kaifeng Wang, Zhiyuan Fu and Ru Huang*, “New insights into memory window of Ferroelectric FET impacted by read operations with awareness of polarization switching dynamics”, IEEE Trans. Electron Devices, vol. 69, no. 9, pp. 5310-5315, 2022.
  • Jin Luo#, Weikai Xu#, Boyi Fu, Zheru Yu, Mengxuan Yang, Yiqing Li, Qianqian Huang*, and Ru Huang*, “A Novel Ambipolar Ferroelectric Tunnel FinFET based Content Addressable Memory with Ultra-low Hardware Cost and High Energy Efficiency for Machine Learning”, in VLSI Symp. Tech. Dig., 2022.
  • Weikai Xu, Jin Luo, Yide Du, Qianqian Huang*, and Ru Huang*, “Novel negative-feedback method for writing variation suppression in FeFET-based computing-in-memory macro”, in CSTIC, Shanghai, China, June, 2022. (Best Student Paper Award)
  • Jin Luo, Tianyi Liu, Zhiyuan Fu, Xinming Wei, Mengxuan Yang, Liang Chen, Qianqian Huang*, and Ru Huang*, “A Novel FeFET-based Adaptively-Stochastic Neuron for Stimulated-Annealing based Optimizer with Reduced Hardware Cost”, IEEE Electron Device Lett., vol. 43, no. 2, pp. 308-311, 2022.
  • Jin Luo, Cheng Chen, Qianqian Huang*, and Ru Huang*, “A Biomimetic Tunnel FET-based Spiking Neuron for Energy Efficient Neuromorphic Computing with Reduced Hardware Cost”, IEEE Trans. Electron Devices, vol. 69, no. 2, pp. 882-886, 2022.
  • Jin Luo, Weikai Xu, Yide Du, Boyi Fu, Jiahao Song, Zhiyuan Fu, Mengxuan Yang, Yiqing Li, Le Ye, Qianqian Huang* and Ru Huang*, “Energy- and Area-efficient Fe-FinFET-based Time-Domain Mixed-Signal Computing In Memory for Edge Machine Learning”, in IEDM Tech. Dig., 2021, pp 438-441.
  • Zhixuan Wang, Le Ye*, Qianqian Huang*, Yangyuan Wang and Ru Huang “Re-Assessment of Steep-Slope Device Design from a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-less Method”, IEEE TCAS-I, vol. 68, no. 4, pp. 1624-1635, 2021.
  • Liang Chen, Rundong Jia, Qianqian Huang*, Ru Huang*, “Si/SnS2 vertical heterojunction tunneling transistor with ionic-liquid gate for ultra-low power application”, in CSTIC, Shanghai, China, March, 2021. (Best Student Paper Award)
  • Kaifeng Wang, Qianqian Huang*, Chang Su, Liang Chen, Mengxuan Yang, Ru Huang*, “Impacts of ferroelectric parameters on the electrical characteristics of FeFET for low-power logic and memory applications”, in CSTIC, Shanghai, China, March, 2021. (Best Poster Award)
  • Yiqing Li, Qianqian Huang*, Mengxuan Yang, Ting Li, Zhixuan Wang, Weihai Bu, Jin Kang, Wenbo Wang, Shengdong Zhang, and Ru Huang*, “A Novel Self-Aligned Dopant-Segregated Schottky Tunnel-FET with Asymmetry Sidewall Based on Standard CMOS Technology”, in ICSICT, Kun Ming, China, 2020. (Best Student Paper Award)
  • Shuhan Liu, Tianyi Liu, Zhiyuan Fu, Cheng Chen, Qianqian Huang*, Ru Huang*, “Implementation of lateral divisive inhibition based on ferroelectric FET with ultra-low hardware cost for neuromorphic computing”, in CSTIC, Shanghai, China, June, 2020. (Best Student Paper Award)
  • Jin Luo, Liutao Yu, Tianyi Liu, Mengxuan Yang, Zhiyuan Fu, Zhongxin Liang, Liang Chen, Cheng Chen, Shuhan Liu, Si Wu, Qianqian Huang*, Ru Huang*, “Capacitor-less Stochastic Leaky-FeFET Neuron of Both Excitatory and Inhibitory Connections for SNN with Reduced Hardware Cost”, in IEDM Tech. Dig., 2019.
  • Cheng Chen, Mengxuan Yang, Shuhan Liu, Tianyi Liu, Kunkun Zhu, Yang Zhao, Huimin Wang, Qianqian Huang* and Ru Huang*, “Bio-Inspired Neurons Based on Novel Leaky-FeFET with Ultra-Low Hardware Cost and Advanced Functionality for All-Ferroelectric Neural Network”, in VLSI Symp. Tech. Dig., 2019.
  • Yang Zhao, Zhongxin Liang, Qianqian Huang*, Cheng Chen, Mengxuan Yang, Zixuan Sun, Kunkun Zhu, Huimin Wang, Shuhan Liu, Tianyi Liu, Yue Peng, Genquan Han and Ru Huang*, “A Novel Negative Capacitance Tunnel FET with Improved Subthreshold Swing and Nearly Non-Hysteresis through Hybrid Modulation”, IEEE Electron Device Lett., vol. 40, no. 6, 2019, pp. 989-992.
  • Zhixuan Wang, Yuan Zhong, Cheng Chen, Qianqian Huang*, Le Ye*, Libo Yang, Yangyuan Wang, Ru Huang, “Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance”, ISCAS, Sapporo, Japan, May 2019.
  • Kunkun Zhu, Qianqian Huang*, Huimin Wang, Mengxuan Yang, Yang Zhao, Ru Huang*, “Investigation of Negative Capacitance Effect from Domain Switching Dynamics”, in CSTIC, Shanghai, China, March, 2019. (Best Student Paper Award)
  • Huimin Wang, Mengxuan Yang, Qianqian Huang*, Kunkun Zhu, Yang Zhao, Zhongxin Liang, Cheng Chen, Zhixuan Wang, Yuan Zhong, Xing Zhang, Ru Huang*, “New Insights into the Physical Origin of Negative Capacitance and Hysteresis in NCFETs”, in IEDM Tech. Dig., 2018, pp. 707-710.
  • Jiaxin Wang, Rundong Jia, Qianqian Huang*, Chen Pan, Jiadi Zhu, Huimin Wang, Cheng Chen, Yawen Zhang, Yuchao Yang, Haisheng Song, Feng Miao, Ru Huang*, “Vertical WS2/SnS2 van der Waals Heterostructure for Tunneling Transistors”, Scientific Reports, 8, 17755 (2018).
  • Yawen Zhang, Jiewen Fan, Qianqian Huang*, Jiadi Zhu, Yang Zhao, Ming Li, Yanqing Wu, Ru Huang*, “Voltage-Controlled Magnetoresistance in Silicon Nanowire Transistors”, Scientific Reports, 8, 15194 (2018).
  • Cheng Chen, Qianqian Huang*, Jiadi Zhu, Zhixuan Wang, Yang Zhao, Rundong Jia, Lingyi Guo, Ru Huang*, “New Insights into Energy Efficiency of Tunnel FET with Awareness of Source-Doping-Gradient Variation”, IEEE Trans. Electron Devices, vol. 65, no. 5, pp.2003-2009, 2018.
  • Cheng Chen, Qianqian Huang*, Jiadi Zhu, Yang Zhao, Lingyi Guo, Ru Huang*, “New Understanding of Random Telegraph Noise Amplitude in Tunnel FETs”, IEEE Trans. Electron Devices, vol. 64, no. 8, pp. 3324-3330, 2017.
  • Jiadi Zhu, Yang Zhao, Qianqian Huang*, Cheng Chen, Chunlei Wu, Rundong Jia, and Ru Huang*, “Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET with High ION/IOFF Ratio and Steep Swing”, IEEE Electron Device Lett., vol. 38, no. 9, pp. 1200-1203, 2017.
  • Jiadi Zhu, Qianqian Huang*, Lingyi Guo, Libo Yang, Cheng Chen, Le Ye and Ru Huang*, “Benchmarking of multi-finger Schottky-barrier tunnel FET for ultra-low power applications”, in CSTIC, Shanghai, China, March, 2018. (Best Poster Award)
  • Yang Zhao, Chunlei Wu, Qianqian Huang*, Cheng Chen, Jiadi Zhu, Lingyi Guo, Rundong Jia, Zhu lv, Yuchao Yang, Ming Li*, Ru Huang*, “A Novel Tunnel FET Design through Adaptive Bandgap Engineering with Constant Sub-threshold Slope over 5 Decades of Current and High ION/IOFF Ratio”, IEEE Electron Device Lett., vol. 39, no. 5, 2017, pp. 540-543.
  • Qianqian Huang, Rundong Jia, Jiadi Zhu, Zhu Lv, Jiaxin Wang, Cheng Chen, Yang Zhao, Runsheng Wang, Weihai Bu, Wenbo Wang, Jin Kang, Kelu Hua, Hanming Wu, Shaofeng Yu, Yangyuan Wang, Ru Huang, “Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization”, in IEDM Tech. Dig., 2016, pp. 782-785.
  • Qianqian Huang, Rundong Jia, Cheng Chen, Hao Zhu, Lingyi Guo, Junyao Wang, Jiaxin Wang, Chunlei Wu, Runsheng Wang, Weihai Bu, Jing Kang, Wenbo Wang, Hanming Wu, Shiuh-Wuu Lee, Yangyuan Wang, Ru Huang, “First Foundry Platform of Complementary Tunnel-FETs in CMOS Baseline Technology for Ultralow-Power IoT Applications: Manufacturability, Variability and Technology Roadmap”, in IEDM Tech. Dig., 2015, pp. 604-607.
  • Qianqian Huang, Ru Huang, Chunlei Wu, Hao Zhu, Cheng Chen, Jiaxin Wang, Lingyi Guo, Runsheng Wang, Le Ye and Yangyuan Wang, “Comprehensive Performance Re-assessment of TFETs with a Novel Design by Gate and Source Engineering from Device/Circuit Perspective”, in IEDM Tech. Dig., 2014, pp. 335 - 338.
  • Qianqian Huang, Ru Huang, Cheng Chen, Chunlei Wu, Jiaxin Wang, Chao Wang, Yangyuan Wang, “Deep Insights into Low Frequency Noise Behavior of Tunnel FETs with Source Junction Engineering”, in VLSI Symp. Tech. Dig., 2014, pp. 88-89.
  • Qianqian Huang, Ru Huang, Yue Pan, Shenghu Tan, Yangyuan Wang, “Resistive-Gate Field-Effect Transistor: a Novel Steep-Slope Device Based on a Metal-Insulator-Metal-Oxide Gate Stack”, IEEE Electron Device Lett.,vol. 35, no. 8, pp. 877-879, 2014.
  • Qianqian Huang, Ru Huang, Shaowen Chen, Jundong Wu, Zhan Zhan, Yingxin Qiu, and Yangyuan Wang, “Device physics and design of T-gate Schottky barrier tunnel FET with adaptive operation mechanism,” Semicond. Sci. Tech.,vol.29, no. 9, pp. 095013, 2014. (IOP select)
  • Qianqian Huang, Ru Huang, Zhan Zhan, Yingxin Qiu, Wenzhe Jiang, Chunlei Wu, Yangyuan Wang, “A Novel Si Tunnel FET with 36mV/dec Subthreshold Slope Based on Junction Depleted-Modulation through Striped Gate Configuration”, in IEDM Tech. Dig., 2012, pp. 187 - 190.
  • Qianqian Huang, Zhan Zhan, Ru Huang , Xiang Mao, Lijie Zhang, Yingxin Qiu, Yangyuan Wang, "Self-Depleted T-gate Schottky Barrier Tunneling FET with Low Average Subthreshold Slope and High ION/IOFF by Gate Configuration and Barrier Modulation", in IEDM Tech. Dig., 2011, pp. 382-385.
  • Qianqian Huang, Ru Huang, Zhenhua Wang, Zhan Zhan, and Yangyuan Wang, "Schottky barrier impact-ionization metal-oxide-semiconductor device with reduced operating voltage", Appl. Phys. Lett., 99, 083507 (2011).

部分主持科研项目

  • 国家重点研发计划专项项目课题
  • 国家自然科学基金应急管理项目
  • 国家自然科学基金优秀青年科学基金项目
  • 国家自然科学基金青年科学基金项目
  • 中国博士后科学基金特别资助项目

部分奖励与荣誉

  • 2023年 第十八届中国青年女科学家奖
  • 2022年 北京大学优秀班主任
  • 2022年 北京市普通高校本科毕业设计优秀指导教师
  • 2021年 北京大学本科生科研训练优秀指导教师奖
  • 2021年 北京脑科学与类脑研究中心青年学者
  • 2021年 北京大学第二十一届青年教师教学基本功比赛一等奖、优秀教案奖、最佳教学演示奖
  • 2020年 腾讯基金会科学探索奖
  • 2020年 求是科技基金会求是杰出青年学者奖
  • 2020年 中国电子学会优秀科技工作者荣誉称号
  • 2019年 北京大学杨芙清-王阳元院士教师奖优秀奖
  • 2019年 IEEE Electron Devices Society Early Career Award
  • 2019年 北京市科技新星计划
  • 2019年 福布斯中国30岁以下精英榜
  • 2019年 北京大学博雅青年学者人才计划
  • 2018年 国家优秀青年科学基金项目资助
  • 2017年 未来女科学家计划
  • 2016年 北京大学优秀博士后荣誉称号
  • 2016年 北京大学博雅博士后
  • 2016年 中国电子学会优秀博士论文
  • 2015年 北京大学优秀博士学位论文
  • 2015年 北京市普通高等学校优秀毕业生
  • 2015年 北京大学优秀毕业生荣誉称号
  • 2015年 北京大学研究生学术十杰荣誉称号
  • 2014年 北京大学信息科学技术学院学术十杰荣誉称号
  • 2012-2014学年 北京大学国家奖学金
  • 2012年 教育部博士研究生学术新人奖
  • 2010-2015学年 北京大学博士研究生校长奖学金