The paper "9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined‑SAR ADC with Continuous‑Time SAR‑Assisted Detect‑and‑Skip and Open‑then‑Close Correlated Level Shifting" has been selected as the highlight paper of the session. Cheers!
Congrats to Siyuan Ye, and whole team!
We will present the total 3 papers in ISSCC 2024 (2024/2/18-2024/2/24). We welcome you to join us and look forward to meeting you in San Francisco.
One 12nm agile-designed SoC is designed with decentralized power management (work done at Harvard), and a 22nm 0.26nW/synapse SNN accelerator will be presented (collaborated with Prof. Le Ye).